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lavc/vc1dsp: match C block layout in inv_trans_4x4_rvv

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Although checkasm does not verify this, the decoder requires that the
transform updates the input block exactly like the C code does.

This fixes vc1-ism, vc1_ilaced_twomv, vc1_sa00040, vc1_sa10091,
vc1_sa10143, vc1_sa20021, vc1test_smm0005 and wmv3-drm-dec tests.
This commit is contained in:
Rémi Denis-Courmont 2024-06-10 20:29:56 +03:00
parent 6ae1a337f2
commit 6c05069e68
1 changed files with 4 additions and 4 deletions
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8
libavcodec/riscv/vc1dsp_rvv.S
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@ -380,12 +380,12 @@ func ff_vc1_inv_trans_4x4_rvv, zve32x
vlsseg4e16.v v0, (a2), a3
li t1, 3
jal t0, ff_vc1_inv_trans_4_rvv
vsseg4e16.v v0, (a2)
addi t1, a2, 1 * 4 * 2
vssseg4e16.v v0, (a2), a3
addi t1, a2, 2 * 4 * 2
vle16.v v0, (a2)
addi t2, a2, 2 * 4 * 2
addi t2, a2, 4 * 4 * 2
vle16.v v1, (t1)
addi t3, a2, 3 * 4 * 2
addi t3, a2, 6 * 4 * 2
vle16.v v2, (t2)
vle16.v v3, (t3)
li t1, 7