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yadif: x86: fix build for compilers without aligned stack
Manually load registers to avoid using 8 registers on x86_32 with compilers that do not align the stack (e.g. MSVC). Signed-off-by: Diego Biurrun <diego@biurrun.de>
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e28ac6e5e2
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@ -31,8 +31,8 @@ pw_1: times 8 dw 1
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SECTION .text
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%macro CHECK 2
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movu m2, [curq+mrefsq+%1]
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movu m3, [curq+prefsq+%2]
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movu m2, [curq+t1+%1]
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movu m3, [curq+t0+%2]
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mova m4, m2
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mova m5, m2
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pxor m4, m3
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@ -97,8 +97,8 @@ SECTION .text
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%macro FILTER 3
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.loop%1:
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pxor m7, m7
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LOAD 0, [curq+mrefsq]
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LOAD 1, [curq+prefsq]
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LOAD 0, [curq+t1]
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LOAD 1, [curq+t0]
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LOAD 2, [%2]
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LOAD 3, [%3]
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mova m4, m3
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@ -109,8 +109,8 @@ SECTION .text
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mova [rsp+32], m1
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psubw m2, m4
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ABS1 m2, m4
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LOAD 3, [prevq+mrefsq]
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LOAD 4, [prevq+prefsq]
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LOAD 3, [prevq+t1]
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LOAD 4, [prevq+t0]
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psubw m3, m0
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psubw m4, m1
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ABS1 m3, m5
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@ -119,8 +119,8 @@ SECTION .text
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psrlw m2, 1
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psrlw m3, 1
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pmaxsw m2, m3
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LOAD 3, [nextq+mrefsq]
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LOAD 4, [nextq+prefsq]
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LOAD 3, [nextq+t1]
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LOAD 4, [nextq+t0]
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psubw m3, m0
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psubw m4, m1
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ABS1 m3, m5
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@ -136,8 +136,8 @@ SECTION .text
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psrlw m1, 1
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ABS1 m0, m2
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movu m2, [curq+mrefsq-1]
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movu m3, [curq+prefsq-1]
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movu m2, [curq+t1-1]
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movu m3, [curq+t0-1]
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mova m4, m2
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psubusb m2, m3
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psubusb m3, m4
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@ -164,12 +164,12 @@ SECTION .text
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CHECK2
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mova m6, [rsp+48]
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cmp DWORD modem, 2
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cmp DWORD r8m, 2
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jge .end%1
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LOAD 2, [%2+mrefsq*2]
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LOAD 4, [%3+mrefsq*2]
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LOAD 3, [%2+prefsq*2]
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LOAD 5, [%3+prefsq*2]
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LOAD 2, [%2+t1*2]
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LOAD 4, [%3+t1*2]
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LOAD 3, [%2+t0*2]
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LOAD 5, [%3+t0*2]
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paddw m2, m4
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paddw m3, m5
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psrlw m2, 1
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@ -208,19 +208,31 @@ SECTION .text
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add prevq, mmsize/2
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add curq, mmsize/2
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add nextq, mmsize/2
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sub wd, mmsize/2
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sub DWORD r4m, mmsize/2
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jg .loop%1
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%endmacro
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%macro YADIF 0
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cglobal yadif_filter_line, 7, 7, 8, 16*5, dst, prev, cur, next, w, prefs, \
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mrefs, parity, mode
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test wq, wq
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%if ARCH_X86_32
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cglobal yadif_filter_line, 4, 6, 8, 80, dst, prev, cur, next, w, prefs, \
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mrefs, parity, mode
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%else
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cglobal yadif_filter_line, 4, 7, 8, 80, dst, prev, cur, next, w, prefs, \
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mrefs, parity, mode
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%endif
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cmp DWORD wm, 0
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jle .ret
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movsxdifnidn prefsq, prefsd
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movsxdifnidn mrefsq, mrefsd
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%if ARCH_X86_32
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mov r4, r5mp
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mov r5, r6mp
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DECLARE_REG_TMP 4,5
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%else
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movsxd r5, DWORD r5m
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movsxd r6, DWORD r6m
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DECLARE_REG_TMP 5,6
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%endif
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cmp DWORD paritym, 0
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cmp DWORD paritym, 0
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je .parity0
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FILTER 1, prevq, curq
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jmp .ret
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