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configure: check if assembler supports RV zicbop

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zicbop is the Cache Block Operation, Prefetch extension to RVI.
This commit is contained in:
Rémi Denis-Courmont 2022-09-23 18:09:18 +03:00
parent 324eba69f7
commit 4570b9f3c4
1 changed files with 4 additions and 0 deletions
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4
configure vendored
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@ -2218,6 +2218,7 @@ ARCH_EXT_LIST_PPC="
ARCH_EXT_LIST_RISCV=" ARCH_EXT_LIST_RISCV="
rv rv
rvv rvv
rv_zicbop
rv_zvbb rv_zvbb
" "
@ -2763,6 +2764,7 @@ power8_deps="vsx"
rv_deps="riscv" rv_deps="riscv"
rvv_deps="rv" rvv_deps="rv"
rv_zicbop="riscv"
rv_zvbb_deps="rvv" rv_zvbb_deps="rvv"
loongson2_deps="mips" loongson2_deps="mips"
@ -6366,6 +6368,7 @@ elif enabled riscv; then
enabled rv && check_inline_asm rv '".option arch, +zbb\nrev8 t0, t1"' enabled rv && check_inline_asm rv '".option arch, +zbb\nrev8 t0, t1"'
enabled rvv && check_inline_asm rvv '".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"' enabled rvv && check_inline_asm rvv '".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"'
enabled rv_zicbop && check_inline_asm rv_zicbop '".option arch, +zicbop\nprefetch.r 64(a0)"'
enabled rv_zvbb && check_inline_asm rv_zvbb '".option arch, +zvbb\nvclz.v v0, v8"' enabled rv_zvbb && check_inline_asm rv_zvbb '".option arch, +zvbb\nvclz.v v0, v8"'
elif enabled x86; then elif enabled x86; then
@ -7922,6 +7925,7 @@ if enabled loongarch; then
echo "LASX enabled ${lasx-no}" echo "LASX enabled ${lasx-no}"
fi fi
if enabled riscv; then if enabled riscv; then
echo "RISC-V CBO Prefetch ${rv_zicbop-no}"
echo "RISC-V Vector enabled ${rvv-no}" echo "RISC-V Vector enabled ${rvv-no}"
fi fi
echo "debug symbols ${debug-no}" echo "debug symbols ${debug-no}"