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Merge remote-tracking branch 'qatar/master'
* qatar/master: log: Include io.h on windows lavr: x86: merge some branches x86: cpu: whitespace (mostly) cosmetics x86: fft: win64: fix stack alignment for memcpy() call Conflicts: libavutil/log.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
commit
3b0ad040b3
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@ -641,19 +641,21 @@ cglobal fft_permute, 2,7,1
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%if ARCH_X86_64
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mov r0, r1
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mov r1, r5
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%endif
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%if WIN64
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sub rsp, 8
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call memcpy
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add rsp, 8
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RET
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%elif ARCH_X86_64
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jmp memcpy
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%else
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push r2
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push r5
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push r1
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%endif
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%if ARCH_X86_64 && WIN64 == 0
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jmp memcpy
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%else
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call memcpy
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%if ARCH_X86_32
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add esp, 12
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%endif
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REP_RET
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RET
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%endif
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cglobal imdct_calc, 3,5,3
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@ -53,14 +53,6 @@ av_cold void ff_audio_convert_init_x86(AudioConvert *ac)
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_FLTP,
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6, 1, 4, "MMX", ff_conv_fltp_to_flt_6ch_mmx);
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}
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if (mm_flags & AV_CPU_FLAG_SSE4 && HAVE_SSE) {
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_FLTP,
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6, 16, 4, "SSE4", ff_conv_fltp_to_flt_6ch_sse4);
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}
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if (mm_flags & AV_CPU_FLAG_AVX && HAVE_AVX) {
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_FLTP,
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6, 16, 4, "AVX", ff_conv_fltp_to_flt_6ch_avx);
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}
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if (mm_flags & AV_CPU_FLAG_SSE2 && HAVE_SSE) {
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if (!(mm_flags & AV_CPU_FLAG_SSE2SLOW)) {
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_S16, AV_SAMPLE_FMT_S32,
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@ -80,12 +72,16 @@ av_cold void ff_audio_convert_init_x86(AudioConvert *ac)
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if (mm_flags & AV_CPU_FLAG_SSE4 && HAVE_SSE) {
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_S16,
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0, 16, 8, "SSE4", ff_conv_s16_to_flt_sse4);
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_FLTP,
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6, 16, 4, "SSE4", ff_conv_fltp_to_flt_6ch_sse4);
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}
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if (mm_flags & AV_CPU_FLAG_AVX && HAVE_AVX) {
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_S32,
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0, 32, 16, "AVX", ff_conv_s32_to_flt_avx);
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_S32, AV_SAMPLE_FMT_FLT,
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0, 32, 32, "AVX", ff_conv_flt_to_s32_avx);
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ff_audio_convert_set_func(ac, AV_SAMPLE_FMT_FLT, AV_SAMPLE_FMT_FLTP,
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6, 16, 4, "AVX", ff_conv_fltp_to_flt_6ch_avx);
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}
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#endif
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}
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@ -40,6 +40,7 @@ static int flags;
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#if defined(_WIN32) && !defined(__MINGW32CE__)
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#include <windows.h>
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#include <io.h>
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static const uint8_t color[16 + AV_CLASS_CATEGORY_NB] = {
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[AV_LOG_PANIC /8] = 12,
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[AV_LOG_FATAL /8] = 12,
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@ -26,16 +26,15 @@
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#include "libavutil/cpu.h"
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/* ebx saving is necessary for PIC. gcc seems unable to see it alone */
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#define cpuid(index,eax,ebx,ecx,edx)\
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__asm__ volatile\
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("mov %%"REG_b", %%"REG_S"\n\t"\
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"cpuid\n\t"\
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"xchg %%"REG_b", %%"REG_S\
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: "=a" (eax), "=S" (ebx),\
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"=c" (ecx), "=d" (edx)\
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: "0" (index));
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#define cpuid(index, eax, ebx, ecx, edx) \
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__asm__ volatile ( \
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"mov %%"REG_b", %%"REG_S" \n\t" \
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"cpuid \n\t" \
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"xchg %%"REG_b", %%"REG_S \
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: "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
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: "0" (index))
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#define xgetbv(index,eax,edx) \
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#define xgetbv(index, eax, edx) \
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
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/* Function to test if multimedia instructions are supported... */
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@ -43,8 +42,8 @@ int ff_get_cpu_flags_x86(void)
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{
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int rval = 0;
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int eax, ebx, ecx, edx;
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int max_std_level, max_ext_level, std_caps=0, ext_caps=0;
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int family=0, model=0;
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int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
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int family = 0, model = 0;
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union { int i[3]; char c[12]; } vendor;
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#if ARCH_X86_32
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@ -79,19 +78,20 @@ int ff_get_cpu_flags_x86(void)
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vendor.i[1] = edx;
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vendor.i[2] = ecx;
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if(max_std_level >= 1){
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if (max_std_level >= 1) {
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cpuid(1, eax, ebx, ecx, std_caps);
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family = ((eax>>8)&0xf) + ((eax>>20)&0xff);
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model = ((eax>>4)&0xf) + ((eax>>12)&0xf0);
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family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
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model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0);
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if (std_caps & (1 << 15))
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rval |= AV_CPU_FLAG_CMOV;
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if (std_caps & (1<<23))
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if (std_caps & (1 << 23))
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rval |= AV_CPU_FLAG_MMX;
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if (std_caps & (1<<25))
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rval |= AV_CPU_FLAG_MMX2
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if (std_caps & (1 << 25))
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rval |= AV_CPU_FLAG_MMX2;
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#if HAVE_SSE
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| AV_CPU_FLAG_SSE;
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if (std_caps & (1<<26))
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if (std_caps & (1 << 25))
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rval |= AV_CPU_FLAG_SSE;
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if (std_caps & (1 << 26))
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rval |= AV_CPU_FLAG_SSE2;
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if (ecx & 1)
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rval |= AV_CPU_FLAG_SSE3;
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@ -111,20 +111,19 @@ int ff_get_cpu_flags_x86(void)
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}
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#endif
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#endif
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;
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}
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cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
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if(max_ext_level >= 0x80000001){
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if (max_ext_level >= 0x80000001) {
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cpuid(0x80000001, eax, ebx, ecx, ext_caps);
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if (ext_caps & (1U<<31))
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if (ext_caps & (1U << 31))
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rval |= AV_CPU_FLAG_3DNOW;
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if (ext_caps & (1<<30))
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if (ext_caps & (1 << 30))
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rval |= AV_CPU_FLAG_3DNOWEXT;
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if (ext_caps & (1<<23))
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if (ext_caps & (1 << 23))
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rval |= AV_CPU_FLAG_MMX;
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if (ext_caps & (1<<22))
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if (ext_caps & (1 << 22))
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rval |= AV_CPU_FLAG_MMX2;
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/* Allow for selectively disabling SSE2 functions on AMD processors
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if (!strncmp(vendor.c, "GenuineIntel", 12)) {
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if (family == 6 && (model == 9 || model == 13 || model == 14)) {
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/* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")
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* theoretically support sse2, but it's usually slower than mmx,
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* so let's just pretend they don't. AV_CPU_FLAG_SSE2 is disabled and
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* AV_CPU_FLAG_SSE2SLOW is enabled so that SSE2 is not used unless
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* explicitly enabled by checking AV_CPU_FLAG_SSE2SLOW. The same
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* situation applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
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if (rval & AV_CPU_FLAG_SSE2) rval ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2;
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if (rval & AV_CPU_FLAG_SSE3) rval ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3;
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/* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
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* 6/14 (core1 "yonah") theoretically support sse2, but it's
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* usually slower than mmx, so let's just pretend they don't.
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* AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
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* enabled so that SSE2 is not used unless explicitly enabled
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* by checking AV_CPU_FLAG_SSE2SLOW. The same situation
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* applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
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if (rval & AV_CPU_FLAG_SSE2)
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rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
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if (rval & AV_CPU_FLAG_SSE3)
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rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
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}
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/* The Atom processor has SSSE3 support, which is useful in many cases,
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* but sometimes the SSSE3 version is slower than the SSE2 equivalent
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