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Revert "avcodec/nvenc: make hw_frames_ctx fully optional"

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This reverts commit 7d4e1f7cfb.

Accidentially pushed this with a batch of other patches, and it didn't
seem to break anything, so I went with it.
Except it does, so reverting it it is.
This commit is contained in:
Timo Rothenpieler 2018-05-07 22:39:20 +02:00
parent 07d9c31055
commit 2e700b082c
1 changed files with 15 additions and 22 deletions
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37
libavcodec/nvenc.c
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@ -1486,21 +1486,19 @@ av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
int ret;
if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) {
if (avctx->hw_frames_ctx) {
AVHWFramesContext *frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
if (frames_ctx->format != avctx->pix_fmt) {
av_log(avctx, AV_LOG_ERROR,
"hw_frames_ctx must match the GPU frame type\n");
return AVERROR(EINVAL);
}
ctx->data_pix_fmt = frames_ctx->sw_format;
} else if (avctx->sw_pix_fmt && avctx->sw_pix_fmt != AV_PIX_FMT_NONE) {
ctx->data_pix_fmt = avctx->sw_pix_fmt;
} else {
AVHWFramesContext *frames_ctx;
if (!avctx->hw_frames_ctx) {
av_log(avctx, AV_LOG_ERROR,
"either hw_frames_ctx or sw_pix_fmt is required for hw frame input\n");
"hw_frames_ctx must be set when using GPU frames as input\n");
return AVERROR(EINVAL);
}
frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
if (frames_ctx->format != avctx->pix_fmt) {
av_log(avctx, AV_LOG_ERROR,
"hw_frames_ctx must match the GPU frame type\n");
return AVERROR(EINVAL);
}
ctx->data_pix_fmt = frames_ctx->sw_format;
} else {
ctx->data_pix_fmt = avctx->pix_fmt;
}
@ -1603,15 +1601,10 @@ static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
enum AVPixelFormat sw_format = ctx->data_pix_fmt;
AVHWFramesContext *frames_ctx = (AVHWFramesContext*)frame->hw_frames_ctx->data;
NV_ENC_REGISTER_RESOURCE reg;
int i, idx, ret;
if (frame->hw_frames_ctx) {
AVHWFramesContext *frames_ctx = (AVHWFramesContext*)frame->hw_frames_ctx->data;
sw_format = frames_ctx->sw_format;
}
for (i = 0; i < ctx->nb_registered_frames; i++) {
if (avctx->pix_fmt == AV_PIX_FMT_CUDA && ctx->registered_frames[i].ptr == frame->data[0])
return i;
@ -1624,8 +1617,8 @@ static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
return idx;
reg.version = NV_ENC_REGISTER_RESOURCE_VER;
reg.width = frame->width;
reg.height = frame->height;
reg.width = frames_ctx->width;
reg.height = frames_ctx->height;
reg.pitch = frame->linesize[0];
reg.resourceToRegister = frame->data[0];
@ -1637,10 +1630,10 @@ static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
reg.subResourceIndex = (intptr_t)frame->data[1];
}
reg.bufferFormat = nvenc_map_buffer_format(sw_format);
reg.bufferFormat = nvenc_map_buffer_format(frames_ctx->sw_format);
if (reg.bufferFormat == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
av_get_pix_fmt_name(sw_format));
av_get_pix_fmt_name(frames_ctx->sw_format));
return AVERROR(EINVAL);
}