mirror of https://git.ffmpeg.org/ffmpeg.git
Revert "avcodec/nvenc: make hw_frames_ctx fully optional"
This reverts commit 7d4e1f7cfb
.
Accidentially pushed this with a batch of other patches, and it didn't
seem to break anything, so I went with it.
Except it does, so reverting it it is.
This commit is contained in:
parent
07d9c31055
commit
2e700b082c
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@ -1486,21 +1486,19 @@ av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
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int ret;
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if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) {
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if (avctx->hw_frames_ctx) {
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AVHWFramesContext *frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
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if (frames_ctx->format != avctx->pix_fmt) {
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av_log(avctx, AV_LOG_ERROR,
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"hw_frames_ctx must match the GPU frame type\n");
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return AVERROR(EINVAL);
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}
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ctx->data_pix_fmt = frames_ctx->sw_format;
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} else if (avctx->sw_pix_fmt && avctx->sw_pix_fmt != AV_PIX_FMT_NONE) {
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ctx->data_pix_fmt = avctx->sw_pix_fmt;
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} else {
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AVHWFramesContext *frames_ctx;
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if (!avctx->hw_frames_ctx) {
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av_log(avctx, AV_LOG_ERROR,
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"either hw_frames_ctx or sw_pix_fmt is required for hw frame input\n");
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"hw_frames_ctx must be set when using GPU frames as input\n");
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return AVERROR(EINVAL);
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}
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frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
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if (frames_ctx->format != avctx->pix_fmt) {
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av_log(avctx, AV_LOG_ERROR,
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"hw_frames_ctx must match the GPU frame type\n");
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return AVERROR(EINVAL);
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}
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ctx->data_pix_fmt = frames_ctx->sw_format;
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} else {
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ctx->data_pix_fmt = avctx->pix_fmt;
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}
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@ -1603,15 +1601,10 @@ static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
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NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
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NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
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enum AVPixelFormat sw_format = ctx->data_pix_fmt;
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AVHWFramesContext *frames_ctx = (AVHWFramesContext*)frame->hw_frames_ctx->data;
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NV_ENC_REGISTER_RESOURCE reg;
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int i, idx, ret;
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if (frame->hw_frames_ctx) {
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AVHWFramesContext *frames_ctx = (AVHWFramesContext*)frame->hw_frames_ctx->data;
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sw_format = frames_ctx->sw_format;
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}
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for (i = 0; i < ctx->nb_registered_frames; i++) {
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if (avctx->pix_fmt == AV_PIX_FMT_CUDA && ctx->registered_frames[i].ptr == frame->data[0])
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return i;
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@ -1624,8 +1617,8 @@ static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
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return idx;
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reg.version = NV_ENC_REGISTER_RESOURCE_VER;
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reg.width = frame->width;
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reg.height = frame->height;
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reg.width = frames_ctx->width;
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reg.height = frames_ctx->height;
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reg.pitch = frame->linesize[0];
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reg.resourceToRegister = frame->data[0];
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@ -1637,10 +1630,10 @@ static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
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reg.subResourceIndex = (intptr_t)frame->data[1];
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}
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reg.bufferFormat = nvenc_map_buffer_format(sw_format);
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reg.bufferFormat = nvenc_map_buffer_format(frames_ctx->sw_format);
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if (reg.bufferFormat == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
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av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
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av_get_pix_fmt_name(sw_format));
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av_get_pix_fmt_name(frames_ctx->sw_format));
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return AVERROR(EINVAL);
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}
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