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ARM: remove MUL64 and MAC64 inline asm 

Current GCC versions know how to generate these instructions
properly and avoiding inline asm gives better code.  The MULH
function for ARMv5 uses the same instruction and is also not
needed any more.

The MLS64 macro remains since negating an input would normally
not be allowed as it would fail for INT_MIN.  In our uses, the
inputs never have this value and thus negating is safe.

Signed-off-by: Mans Rullgard <mans@mansr.com>
This commit is contained in:
Mans Rullgard 2011-06-05 13:44:28 +01:00
parent 0018b7f043
commit 21c6512542
1 changed files with 1 additions and 30 deletions
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31
libavcodec/arm/mathops.h
View File

@ -28,45 +28,16 @@
#if HAVE_INLINE_ASM #if HAVE_INLINE_ASM
#define MULH MULH
#define MUL64 MUL64
#if HAVE_ARMV6 #if HAVE_ARMV6
#define MULH MULH
static inline av_const int MULH(int a, int b) static inline av_const int MULH(int a, int b)
{ {
int r; int r;
__asm__ ("smmul %0, %1, %2" : "=r"(r) : "r"(a), "r"(b)); __asm__ ("smmul %0, %1, %2" : "=r"(r) : "r"(a), "r"(b));
return r; return r;
} }
static inline av_const int64_t MUL64(int a, int b)
{
int64_t x;
__asm__ ("smull %Q0, %R0, %1, %2" : "=r"(x) : "r"(a), "r"(b));
return x;
}
#else
static inline av_const int MULH(int a, int b)
{
int lo, hi;
__asm__ ("smull %0, %1, %2, %3" : "=&r"(lo), "=&r"(hi) : "r"(b), "r"(a));
return hi;
}
static inline av_const int64_t MUL64(int a, int b)
{
int64_t x;
__asm__ ("smull %Q0, %R0, %1, %2" : "=&r"(x) : "r"(a), "r"(b));
return x;
}
#endif #endif
static inline av_const int64_t MAC64(int64_t d, int a, int b)
{
__asm__ ("smlal %Q0, %R0, %1, %2" : "+r"(d) : "r"(a), "r"(b));
return d;
}
#define MAC64(d, a, b) ((d) = MAC64(d, a, b))
#define MLS64(d, a, b) MAC64(d, -(a), b) #define MLS64(d, a, b) MAC64(d, -(a), b)
#if HAVE_ARMV5TE #if HAVE_ARMV5TE