RepoMirrors
/
ffmpeg
mirror of https://git.ffmpeg.org/ffmpeg.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

lavc/riscv: drop probing for F & D extensions 

F and D extensions are included in all RISC-V application profiles ever
made (so starting from RV64GC a.k.a. RVA20). Realistically they need to be
selected at compilation time.

Currently, there are no consumers for these two flags. If there is ever a
need to reintroduce F- or D-specific optimisations, we can always use
__riscv_f or __riscv_d compiler predefined macros respectively.
This commit is contained in:
Rémi Denis-Courmont 2024-07-25 23:20:05 +03:00
parent 2f083fd581
commit 1b2a925e94
4 changed files with 0 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
libavutil/cpu.c
View File

@ -184,8 +184,6 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
{ "lasx", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX }, .unit = "flags" },
#elif ARCH_RISCV
{ "rvi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI }, .unit = "flags" },
{ "rvf", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF }, .unit = "flags" },
{ "rvd", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD }, .unit = "flags" },
{ "rvb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB }, .unit = "flags" },
{ "zve32x", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I32 }, .unit = "flags" },
{ "zve32f", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" },

12
libavutil/riscv/cpu.c
View File

@ -58,8 +58,6 @@ int ff_get_cpu_flags_riscv(void)
if (__riscv_hwprobe(pairs, FF_ARRAY_ELEMS(pairs), 0, NULL, 0) == 0) {
if (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA)
ret |= AV_CPU_FLAG_RVI;
if (pairs[1].value & RISCV_HWPROBE_IMA_FD)
ret |= AV_CPU_FLAG_RVF | AV_CPU_FLAG_RVD;
#ifdef RISCV_HWPROBE_IMA_V
if (pairs[1].value & RISCV_HWPROBE_IMA_V)
ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
@ -96,10 +94,6 @@ int ff_get_cpu_flags_riscv(void)
if (hwcap & HWCAP_RV('I'))
ret |= AV_CPU_FLAG_RVI;
if (hwcap & HWCAP_RV('F'))
ret |= AV_CPU_FLAG_RVF;
if (hwcap & HWCAP_RV('D'))
ret |= AV_CPU_FLAG_RVD;
if (hwcap & HWCAP_RV('B'))
ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC |
AV_CPU_FLAG_RVB;
@ -114,12 +108,6 @@ int ff_get_cpu_flags_riscv(void)
#ifdef __riscv_i
ret |= AV_CPU_FLAG_RVI;
#endif
#if defined (__riscv_flen) && (__riscv_flen >= 32)
ret |= AV_CPU_FLAG_RVF;
#if (__riscv_flen >= 64)
ret |= AV_CPU_FLAG_RVD;
#endif
#endif
#ifdef __riscv_zba
ret |= AV_CPU_FLAG_RVB_ADDR;

2
libavutil/tests/cpu.c
View File

@ -86,8 +86,6 @@ static const struct {
{ AV_CPU_FLAG_LASX, "lasx" },
#elif ARCH_RISCV
{ AV_CPU_FLAG_RVI, "rvi" },
{ AV_CPU_FLAG_RVF, "rvf" },
{ AV_CPU_FLAG_RVD, "rvd" },
{ AV_CPU_FLAG_RVB_ADDR, "zba" },
{ AV_CPU_FLAG_RVB_BASIC, "zbb" },
{ AV_CPU_FLAG_RVB, "rvb" },

2
tests/checkasm/checkasm.c
View File

@ -291,8 +291,6 @@ static const struct {
#elif ARCH_RISCV
{ "RVI", "rvi", AV_CPU_FLAG_RVI },
{ "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED },
{ "RVF", "rvf", AV_CPU_FLAG_RVF },
{ "RVD", "rvd", AV_CPU_FLAG_RVD },
{ "RVBaddr", "rvb_a", AV_CPU_FLAG_RVB_ADDR },
{ "RVBbasic", "rvb_b", AV_CPU_FLAG_RVB_BASIC },
{ "RVB", "rvb", AV_CPU_FLAG_RVB },