mirror of https://git.ffmpeg.org/ffmpeg.git
x86/hevc_sao: make sao_edge_filter_{10,12} work on x86_32
Reviewed-by: Michael Niedermayer <michaelni@gmx.at> Reviewed-by: Christophe Gisquet <christophe.gisquet@gmail.com> Signed-off-by: James Almer <jamrial@gmail.com>
This commit is contained in:
James Almer
parent
7862325f80
commit
14b44c1614
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@ -293,6 +293,25 @@ HEVC_SAO_BAND_FILTER_16 12, 64, 2
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%define EDGE_SRCSTRIDE 2 * MAX_PB_SIZE + PADDING_SIZE
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%macro HEVC_SAO_EDGE_FILTER_INIT 1
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%if WIN64
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movsxd eoq, dword eom
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%elif ARCH_X86_64
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movsxd eoq, eod
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%else
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mov eoq, r4m
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%endif
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lea tmp2q, [pb_eo]
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movsx a_strideq, byte [tmp2q+eoq*4+1]
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movsx b_strideq, byte [tmp2q+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE>>%1
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imul b_strideq, EDGE_SRCSTRIDE>>%1
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movsx tmpq, byte [tmp2q+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [tmp2q+eoq*4+2]
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add b_strideq, tmpq
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%endmacro
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%macro HEVC_SAO_EDGE_FILTER_COMPUTE_8 1
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pminub m4, m1, m2
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pminub m5, m1, m3
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@ -328,20 +347,7 @@ HEVC_SAO_BAND_FILTER_16 12, 64, 2
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%if ARCH_X86_64
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cglobal hevc_sao_edge_filter_%1_8, 4, 9, 8, dst, src, dststride, offset, eo, a_stride, b_stride, height, tmp
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%define tmp2q heightq
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%if WIN64
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movsxd eoq, dword r4m
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%else
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movsxd eoq, eod
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%endif
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lea tmp2q, [pb_eo]
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movsx a_strideq, byte [tmp2q+eoq*4+1]
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movsx b_strideq, byte [tmp2q+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE
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imul b_strideq, EDGE_SRCSTRIDE
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movsx tmpq, byte [tmp2q+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [tmp2q+eoq*4+2]
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add b_strideq, tmpq
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HEVC_SAO_EDGE_FILTER_INIT 0
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mov heightd, r6m
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%else ; ARCH_X86_32
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@ -350,17 +356,7 @@ cglobal hevc_sao_edge_filter_%1_8, 1, 6, 8, dst, src, dststride, a_stride, b_str
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%define tmpq heightq
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%define tmp2q dststrideq
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%define offsetq heightq
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mov eoq, r4m
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lea tmp2q, [pb_eo]
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movsx a_strideq, byte [tmp2q+eoq*4+1]
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movsx b_strideq, byte [tmp2q+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE
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imul b_strideq, EDGE_SRCSTRIDE
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movsx tmpq, byte [tmp2q+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [tmp2q+eoq*4+2]
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add b_strideq, tmpq
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HEVC_SAO_EDGE_FILTER_INIT 0
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mov srcq, srcm
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mov offsetq, r3m
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mov dststrideq, dststridem
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@ -442,6 +438,7 @@ INIT_YMM cpuname
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paddw m4, m5
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pcmpeqw m2, m4, [pw_m2]
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%if ARCH_X86_64
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pcmpeqw m3, m4, m13
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, m14
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@ -451,6 +448,17 @@ INIT_YMM cpuname
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pand m5, m10
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pand m6, m11
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pand m7, m12
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%else
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pcmpeqw m3, m4, [pw_m1]
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, [pw_1]
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pcmpeqw m7, m4, [pw_2]
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pand m2, [rsp+MMSIZE*0]
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pand m3, [rsp+MMSIZE*1]
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pand m5, [rsp+MMSIZE*2]
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pand m6, [rsp+MMSIZE*3]
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pand m7, [rsp+MMSIZE*4]
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%endif
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paddw m2, m3
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paddw m5, m6
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paddw m2, m7
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@ -461,26 +469,35 @@ INIT_YMM cpuname
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;void ff_hevc_sao_edge_filter_<width>_<depth>_<opt>(uint8_t *_dst, uint8_t *_src, ptrdiff_t stride_dst, int16_t *sao_offset_val,
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; int eo, int width, int height);
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%macro HEVC_SAO_EDGE_FILTER_16 3
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%if ARCH_X86_64
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cglobal hevc_sao_edge_filter_%2_%1, 4, 9, 16, dst, src, dststride, offset, eo, a_stride, b_stride, height, tmp
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%define tmp2q heightq
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%if WIN64
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movsxd eoq, dword r4m
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%else
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movsxd eoq, eod
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%endif
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lea tmp2q, [pb_eo]
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movsx a_strideq, byte [tmp2q+eoq*4+1]
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movsx b_strideq, byte [tmp2q+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE>>1
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imul b_strideq, EDGE_SRCSTRIDE>>1
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movsx tmpq, byte [tmp2q+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [tmp2q+eoq*4+2]
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add b_strideq, tmpq
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HEVC_SAO_EDGE_FILTER_INIT 1
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mov heightd, r6m
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add a_strideq, a_strideq
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add b_strideq, b_strideq
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%else ; ARCH_X86_32
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cglobal hevc_sao_edge_filter_%2_%1, 1, 6, 8, 5*mmsize, dst, src, dststride, a_stride, b_stride, height
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%assign MMSIZE mmsize
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%define eoq srcq
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%define tmpq heightq
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%define tmp2q dststrideq
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%define offsetq heightq
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%define m8 m1
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%define m9 m2
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%define m10 m3
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%define m11 m4
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%define m12 m5
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HEVC_SAO_EDGE_FILTER_INIT 1
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mov srcq, srcm
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mov offsetq, r3m
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mov dststrideq, dststridem
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add a_strideq, a_strideq
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add b_strideq, b_strideq
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%endif ; ARCH
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%if cpuflag(avx2)
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SPLATW m8, [offsetq+2]
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SPLATW m9, [offsetq+4]
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@ -497,9 +514,18 @@ cglobal hevc_sao_edge_filter_%2_%1, 4, 9, 16, dst, src, dststride, offset, eo, a
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SPLATW m12, xm12, 1
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%endif
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pxor m0, m0
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%if ARCH_X86_64
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mova m13, [pw_m1]
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mova m14, [pw_1]
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mova m15, [pw_2]
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%else
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mov heightd, r6m
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mova [rsp+mmsize*0], m8
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mova [rsp+mmsize*1], m9
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mova [rsp+mmsize*2], m10
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mova [rsp+mmsize*3], m11
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mova [rsp+mmsize*4], m12
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%endif
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align 16
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.loop
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@ -573,7 +599,6 @@ HEVC_SAO_EDGE_FILTER_8 48, 1, u
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HEVC_SAO_EDGE_FILTER_8 64, 2, a
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%endif
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%if ARCH_X86_64
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INIT_XMM sse2
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HEVC_SAO_EDGE_FILTER_16 10, 8, 0
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HEVC_SAO_EDGE_FILTER_16 10, 16, 1
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@ -597,4 +622,3 @@ HEVC_SAO_EDGE_FILTER_16 12, 32, 1
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HEVC_SAO_EDGE_FILTER_16 12, 48, 1
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HEVC_SAO_EDGE_FILTER_16 12, 64, 2
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%endif
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%endif
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@ -865,10 +865,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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if (ARCH_X86_64) {
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c->hevc_v_loop_filter_luma = ff_hevc_v_loop_filter_luma_10_sse2;
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c->hevc_h_loop_filter_luma = ff_hevc_h_loop_filter_luma_10_sse2;
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SAO_EDGE_INIT(10, sse2);
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}
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SAO_BAND_INIT(10, sse2);
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SAO_EDGE_INIT(10, sse2);
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c->idct_dc[1] = ff_hevc_idct8x8_dc_10_sse2;
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c->idct_dc[2] = ff_hevc_idct16x16_dc_10_sse2;
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@ -907,10 +906,6 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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c->idct_dc[2] = ff_hevc_idct16x16_dc_10_avx2;
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c->idct_dc[3] = ff_hevc_idct32x32_dc_10_avx2;
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if (ARCH_X86_64) {
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c->sao_edge_filter[2] = ff_hevc_sao_edge_filter_32_10_avx2;
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c->sao_edge_filter[3] = ff_hevc_sao_edge_filter_48_10_avx2;
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c->sao_edge_filter[4] = ff_hevc_sao_edge_filter_64_10_avx2;
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c->put_hevc_epel[5][0][0] = ff_hevc_put_hevc_pel_pixels16_10_avx2;
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c->put_hevc_epel[6][0][0] = ff_hevc_put_hevc_pel_pixels24_10_avx2;
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c->put_hevc_epel[7][0][0] = ff_hevc_put_hevc_pel_pixels32_10_avx2;
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@ -1055,6 +1050,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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c->put_hevc_qpel_bi[9][1][1] = ff_hevc_put_hevc_bi_qpel_hv64_10_avx2;
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}
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SAO_BAND_INIT(10, avx2);
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c->sao_edge_filter[2] = ff_hevc_sao_edge_filter_32_10_avx2;
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c->sao_edge_filter[3] = ff_hevc_sao_edge_filter_48_10_avx2;
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c->sao_edge_filter[4] = ff_hevc_sao_edge_filter_64_10_avx2;
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c->transform_add[2] = ff_hevc_transform_add16_10_avx2;
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c->transform_add[3] = ff_hevc_transform_add32_10_avx2;
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@ -1071,10 +1069,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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if (ARCH_X86_64) {
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c->hevc_v_loop_filter_luma = ff_hevc_v_loop_filter_luma_12_sse2;
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c->hevc_h_loop_filter_luma = ff_hevc_h_loop_filter_luma_12_sse2;
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SAO_EDGE_INIT(12, sse2);
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}
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SAO_BAND_INIT(12, sse2);
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SAO_EDGE_INIT(12, sse2);
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c->idct_dc[1] = ff_hevc_idct8x8_dc_12_sse2;
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c->idct_dc[2] = ff_hevc_idct16x16_dc_12_sse2;
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@ -1107,12 +1104,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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if (EXTERNAL_AVX2(cpu_flags)) {
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c->idct_dc[2] = ff_hevc_idct16x16_dc_12_avx2;
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c->idct_dc[3] = ff_hevc_idct32x32_dc_12_avx2;
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if (ARCH_X86_64) {
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c->sao_edge_filter[2] = ff_hevc_sao_edge_filter_32_12_avx2;
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c->sao_edge_filter[3] = ff_hevc_sao_edge_filter_48_12_avx2;
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c->sao_edge_filter[4] = ff_hevc_sao_edge_filter_64_12_avx2;
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}
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SAO_BAND_INIT(12, avx2);
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c->sao_edge_filter[2] = ff_hevc_sao_edge_filter_32_12_avx2;
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c->sao_edge_filter[3] = ff_hevc_sao_edge_filter_48_12_avx2;
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c->sao_edge_filter[4] = ff_hevc_sao_edge_filter_64_12_avx2;
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}
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}
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}
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