RepoMirrors
/
ffmpeg
mirror of https://git.ffmpeg.org/ffmpeg.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
ffmpeg/libswscale/riscv/Makefile

9 lines
210 B
Makefile
Raw Normal View History

sws/input: R-V V rgb24ToY & bgr24ToY T-Head C908: rgb24_to_y_8_c: 2.0 rgb24_to_y_8_rvv_i32: 2.7 rgb24_to_y_128_c: 26.2 rgb24_to_y_128_rvv_i32: 9.2 rgb24_to_y_1080_c: 219.5 rgb24_to_y_1080_rvv_i32: 76.2 rgb24_to_y_1280_c: 276.2 rgb24_to_y_1280_rvv_i32: 89.7 rgb24_to_y_1920_c: 389.7 rgb24_to_y_1920_rvv_i32: 134.2 SpacemiT X60: rgb24_to_y_8_c: 1.7 rgb24_to_y_8_rvv_i32: 2.2 rgb24_to_y_128_c: 23.2 rgb24_to_y_128_rvv_i32: 4.2 rgb24_to_y_1080_c: 195.0 rgb24_to_y_1080_rvv_i32: 33.7 rgb24_to_y_1280_c: 231.0 rgb24_to_y_1280_rvv_i32: 40.0 rgb24_to_y_1920_c: 346.2 rgb24_to_y_1920_rvv_i32: 59.7
2024-06-04 19:57:33 +00:00
OBJS += riscv/rgb2rgb.o \
riscv/swscale.o
riscv: test for assembler support This should fix the build on LLVM 16 and earlier, at the cost of turning all non-RVV optimisations off.
2023-12-05 15:54:26 +00:00
RV-OBJS += riscv/rgb2rgb_rvb.o
sws/input: R-V V rgb24ToY & bgr24ToY T-Head C908: rgb24_to_y_8_c: 2.0 rgb24_to_y_8_rvv_i32: 2.7 rgb24_to_y_128_c: 26.2 rgb24_to_y_128_rvv_i32: 9.2 rgb24_to_y_1080_c: 219.5 rgb24_to_y_1080_rvv_i32: 76.2 rgb24_to_y_1280_c: 276.2 rgb24_to_y_1280_rvv_i32: 89.7 rgb24_to_y_1920_c: 389.7 rgb24_to_y_1920_rvv_i32: 134.2 SpacemiT X60: rgb24_to_y_8_c: 1.7 rgb24_to_y_8_rvv_i32: 2.2 rgb24_to_y_128_c: 23.2 rgb24_to_y_128_rvv_i32: 4.2 rgb24_to_y_1080_c: 195.0 rgb24_to_y_1080_rvv_i32: 33.7 rgb24_to_y_1280_c: 231.0 rgb24_to_y_1280_rvv_i32: 40.0 rgb24_to_y_1920_c: 346.2 rgb24_to_y_1920_rvv_i32: 59.7
2024-06-04 19:57:33 +00:00
RVV-OBJS += riscv/input_rvv.o \
sws/range_convert: R-V V to/from JPEG C908 X60 chrRangeFromJpeg_8_c: 2.7 2.5 chrRangeFromJpeg_8_rvv_i32: 1.7 1.5 chrRangeFromJpeg_24_c: 7.5 6.7 chrRangeFromJpeg_24_rvv_i32: 1.7 1.5 chrRangeFromJpeg_128_c: 55.2 34.7 chrRangeFromJpeg_128_rvv_i32: 6.5 3.0 chrRangeFromJpeg_144_c: 44.0 39.2 chrRangeFromJpeg_144_rvv_i32: 7.7 4.5 chrRangeFromJpeg_256_c: 78.2 69.5 chrRangeFromJpeg_256_rvv_i32: 12.2 6.0 chrRangeFromJpeg_512_c: 172.2 138.5 chrRangeFromJpeg_512_rvv_i32: 24.5 11.7 chrRangeToJpeg_8_c: 4.7 4.2 chrRangeToJpeg_8_rvv_i32: 2.0 1.7 chrRangeToJpeg_24_c: 13.7 12.2 chrRangeToJpeg_24_rvv_i32: 2.0 1.5 chrRangeToJpeg_128_c: 72.0 63.7 chrRangeToJpeg_128_rvv_i32: 6.7 3.2 chrRangeToJpeg_144_c: 80.7 71.7 chrRangeToJpeg_144_rvv_i32: 8.5 4.7 chrRangeToJpeg_256_c: 143.2 127.2 chrRangeToJpeg_256_rvv_i32: 13.5 6.5 chrRangeToJpeg_512_c: 285.7 253.7 chrRangeToJpeg_512_rvv_i32: 27.0 13.0 lumRangeFromJpeg_8_c: 1.7 1.5 lumRangeFromJpeg_8_rvv_i32: 1.2 1.0 lumRangeFromJpeg_24_c: 4.2 3.7 lumRangeFromJpeg_24_rvv_i32: 1.2 1.0 lumRangeFromJpeg_128_c: 21.7 19.2 lumRangeFromJpeg_128_rvv_i32: 3.7 1.7 lumRangeFromJpeg_144_c: 24.7 22.0 lumRangeFromJpeg_144_rvv_i32: 4.7 2.7 lumRangeFromJpeg_256_c: 43.7 39.0 lumRangeFromJpeg_256_rvv_i32: 7.5 3.2 lumRangeFromJpeg_512_c: 87.0 77.2 lumRangeFromJpeg_512_rvv_i32: 14.5 6.7 lumRangeToJpeg_8_c: 2.7 2.2 lumRangeToJpeg_8_rvv_i32: 1.0 1.0 lumRangeToJpeg_24_c: 7.2 6.5 lumRangeToJpeg_24_rvv_i32: 1.2 1.0 lumRangeToJpeg_128_c: 37.7 33.7 lumRangeToJpeg_128_rvv_i32: 3.7 2.0 lumRangeToJpeg_144_c: 42.5 37.7 lumRangeToJpeg_144_rvv_i32: 4.7 2.7 lumRangeToJpeg_256_c: 75.0 66.7 lumRangeToJpeg_256_rvv_i32: 7.5 3.5 lumRangeToJpeg_512_c: 149.5 133.0 lumRangeToJpeg_512_rvv_i32: 14.7 7.0
2024-06-07 15:36:25 +00:00
riscv/range_rvv.o \
sws/input: R-V V rgb24ToY & bgr24ToY T-Head C908: rgb24_to_y_8_c: 2.0 rgb24_to_y_8_rvv_i32: 2.7 rgb24_to_y_128_c: 26.2 rgb24_to_y_128_rvv_i32: 9.2 rgb24_to_y_1080_c: 219.5 rgb24_to_y_1080_rvv_i32: 76.2 rgb24_to_y_1280_c: 276.2 rgb24_to_y_1280_rvv_i32: 89.7 rgb24_to_y_1920_c: 389.7 rgb24_to_y_1920_rvv_i32: 134.2 SpacemiT X60: rgb24_to_y_8_c: 1.7 rgb24_to_y_8_rvv_i32: 2.2 rgb24_to_y_128_c: 23.2 rgb24_to_y_128_rvv_i32: 4.2 rgb24_to_y_1080_c: 195.0 rgb24_to_y_1080_rvv_i32: 33.7 rgb24_to_y_1280_c: 231.0 rgb24_to_y_1280_rvv_i32: 40.0 rgb24_to_y_1920_c: 346.2 rgb24_to_y_1920_rvv_i32: 59.7
2024-06-04 19:57:33 +00:00
riscv/rgb2rgb_rvv.o
riscv: probe for Zbb extension at load time Due to hysterical raisins, most RISC-V Linux distributions target a RV64GC baseline excluding the Bit-manipulation ISA extensions, most notably: - Zba: address generation extension and - Zbb: basic bit manipulation extension. Most CPUs that would make sense to run FFmpeg on support Zba and Zbb (including the current FATE runner), so it makes sense to optimise for them. In fact a large chunk of existing assembler optimisations relies on Zba and/or Zbb. Since we cannot patch shared library code, the next best thing is to carry a flag initialised at load-time and check it on need basis. This results in 3 instructions overhead on isolated use, e.g.: 1: AUIPC rd, %pcrel_hi(ff_rv_zbb_supported) LBU rd, %pcrel_lo(1b)(rd) BEQZ rd, non_Zbb_fallback_code // Zbb code here The C compiler will typically load the flag ahead of time to reducing latency, and can also keep it around if Zbb is used multiple times in a single optimisation scope. For this to work, the flag symbol must be hidden; otherwise the optimisation degrades with a GOT look-up to support interposition: 1: AUIPC rd, GOT_OFFSET_HI LD rd, GOT_OFFSET_LO(rd) LBU rd, (rd) BEQZ rd, non_Zbb_fallback_code // Zbb code here This patch adds code to provision the flag in libraries using bit manipulation functions from libavutil: byte-swap, bit-weight and counting leading or trailing zeroes.
2024-06-08 07:57:15 +00:00
SHLIBOBJS += riscv/cpu_common.o