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ffmpeg/libavcodec/riscv/sbrdsp_rvv.S

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lavc/sbrdsp: R-V V sum64x5 sum64x5_c: 385.0 sum64x5_rvv_f32: 116.0
2023-10-29 15:39:53 +00:00
/*
* Copyright © 2023 Rémi Denis-Courmont.
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "libavutil/riscv/asm.S"
func ff_sbr_sum64x5_rvv, zve32f
li a5, 64
addi a1, a0, 64 * 4
addi a2, a0, 128 * 4
addi a3, a0, 192 * 4
addi a4, a0, 256 * 4
1:
vsetvli t0, a5, e32, m8, ta, ma
sub a5, a5, t0
vle32.v v0, (a0)
vle32.v v8, (a1)
sh2add a1, t0, a1
vle32.v v16, (a2)
vfadd.vv v0, v0, v8
sh2add a2, t0, a2
vle32.v v24, (a3)
vfadd.vv v0, v0, v16
sh2add a3, t0, a3
vle32.v v8, (a4)
vfadd.vv v0, v0, v24
sh2add a4, t0, a4
vfadd.vv v0, v0, v8
vse32.v v0, (a0)
sh2add a0, t0, a0
bnez a5, 1b
ret
endfunc
lavc/sbrdsp: R-V V sum_square sum_square_c: 803.5 sum_square_rvv_f32: 283.2
2023-10-29 16:10:07 +00:00
func ff_sbr_sum_square_rvv, zve32f
vsetvli t0, zero, e32, m8, ta, ma
slli a1, a1, 1
vmv.v.x v8, zero
vmv.s.x v0, zero
1:
vsetvli t0, a1, e32, m8, tu, ma
vle32.v v16, (a0)
sub a1, a1, t0
vfmacc.vv v8, v16, v16
sh2add a0, t0, a0
bnez a1, 1b
vfredusum.vs v0, v8, v0
vfmv.f.s fa0, v0
NOHWF fmv.x.w a0, fa0
ret
endfunc
lavc/sbrdsp: R-V V neg_odd_64 With 128-bit vectors, this is mostly pointless but also harmless. Performance gains should be more noticeable with larger vector sizes. neg_odd_64_c: 76.2 neg_odd_64_rvv_i64: 74.7
2023-10-29 16:22:08 +00:00
#if __riscv_xlen >= 64
func ff_sbr_neg_odd_64_rvv, zve64x
li a1, 32
li t1, 1 << 63
1:
vsetvli t0, a1, e64, m8, ta, ma
vle64.v v8, (a0)
sub a1, a1, t0
vxor.vx v8, v8, t1
vse64.v v8, (a0)
sh3add a0, t0, a0
bnez t0, 1b
ret
endfunc
#endif
lavc/sbrdsp: R-V V sbr_hf_g_filt hf_g_filt_c: 1552.5 hf_g_filt_rvv_f32: 679.5
2023-10-30 20:03:59 +00:00
lavc/sbrdsp: R-V V autocorrelate With 5 accumulator vectors and 6 inputs, this can only use LMUL=2. Also the number of vector loop iterations is small, just 5 on 128-bit vector hardware. The vector loop is somewhat unusual in that it processes data in descending memory order, in order to save on vector slides: in descending order, we can extract elements to carry over to the next iteration from the bottom of the vectors directly. With ascending order (see in the Opus postfilter function), there are no ways to get the top elements directly. On the downside, this requires the use of separate shift and sub (the would-be SH3SUB instruction does not exist), with a small pipeline stall on the vector load address. The edge cases in scalar are done in scalar as this saves on loads and remains significantly faster than C. autocorrelate_c: 669.2 autocorrelate_rvv_f32: 421.0
2023-11-08 20:17:39 +00:00
func ff_sbr_autocorrelate_rvv, zve32f
vsetvli t0, zero, e32, m4, ta, ma
vmv.v.x v0, zero
flw fa0, (a0)
vmv.v.x v4, zero
flw fa1, 4(a0)
vmv.v.x v8, zero
flw fa2, 8(a0)
li a2, 37
flw fa3, 12(a0)
fmul.s ft10, fa0, fa0
flw fa4, 16(a0)
fmul.s ft6, fa0, fa2
flw fa5, 20(a0)
addi a0, a0, 38 * 8
fmul.s ft7, fa0, fa3
fmul.s ft2, fa0, fa4
fmul.s ft3, fa0, fa5
flw fa0, (a0)
fmadd.s ft10, fa1, fa1, ft10
fmadd.s ft6, fa1, fa3, ft6
flw fa3, 12(a0)
fnmsub.s ft7, fa1, fa2, ft7
flw fa2, 8(a0)
fmadd.s ft2, fa1, fa5, ft2
fnmsub.s ft3, fa1, fa4, ft3
flw fa1, 4(a0)
fmul.s ft4, fa0, fa0
fmul.s ft0, fa0, fa2
fmul.s ft1, fa0, fa3
fmadd.s ft4, fa1, fa1, ft4
fmadd.s ft0, fa1, fa3, ft0
fnmsub.s ft1, fa1, fa2, ft1
1:
vsetvli t0, a2, e32, m2, tu, ma
slli t1, t0, 3
sub a0, a0, t1
vlseg2e32.v v16, (a0)
sub a2, a2, t0
vfmacc.vv v0, v16, v16
vfslide1down.vf v20, v16, fa0
vfmacc.vv v4, v16, v20
vfslide1down.vf v22, v18, fa1
vfmacc.vv v0, v18, v18
vfslide1down.vf v24, v20, fa2
vfmacc.vv v4, v18, v22
vfslide1down.vf v26, v22, fa3
vfmacc.vv v6, v16, v22
vfmv.f.s fa0, v16
vfmacc.vv v8, v16, v24
vfmv.f.s fa1, v18
vfmacc.vv v10, v16, v26
vfmv.f.s fa2, v20
vfnmsac.vv v6, v18, v20
vfmv.f.s fa3, v22
vfmacc.vv v8, v18, v26
vfnmsac.vv v10, v18, v24
bnez a2, 1b
vsetvli t0, zero, e32, m2, ta, ma
vfredusum.vs v0, v0, v2
vfredusum.vs v4, v4, v2
vfmv.f.s fa0, v0
vfredusum.vs v6, v6, v2
vfmv.f.s fa2, v4
fadd.s ft4, ft4, fa0
vfredusum.vs v8, v8, v2
vfmv.f.s fa3, v6
fadd.s ft0, ft0, fa2
vfredusum.vs v10, v10, v2
vfmv.f.s fa4, v8
fadd.s ft1, ft1, fa3
vfmv.f.s fa5, v10
fsw ft0, (a1)
fadd.s ft2, ft2, fa4
fsw ft1, 4(a1)
fadd.s ft3, ft3, fa5
fsw ft2, 8(a1)
fadd.s ft6, ft6, fa2
fsw ft3, 12(a1)
fadd.s ft7, ft7, fa3
fsw ft4, 16(a1)
fadd.s ft10, ft10, fa0
fsw ft6, 24(a1)
fsw ft7, 28(a1)
fsw ft10, 40(a1)
ret
endfunc
lavc/sbrdsp: R-V V sbr_hf_g_filt hf_g_filt_c: 1552.5 hf_g_filt_rvv_f32: 679.5
2023-10-30 20:03:59 +00:00
func ff_sbr_hf_g_filt_rvv, zve32f
li t1, 40 * 2 * 4
sh3add a1, a4, a1
1:
vsetvli t0, a3, e32, m4, ta, ma
vlsseg2e32.v v16, (a1), t1
mul t2, t0, t1
vle32.v v8, (a2)
sub a3, a3, t0
vfmul.vv v16, v16, v8
add a1, t2, a1
vfmul.vv v20, v20, v8
sh2add a2, t0, a2
vsseg2e32.v v16, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc