2024-06-04 19:57:33 +00:00
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/*
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* Copyright © 2024 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_bgr24ToY_rvv, zve32x
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-04 19:57:33 +00:00
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lw t1, 8(a5) # BY
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lw t3, 0(a5) # RY
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j 1f
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endfunc
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2024-07-22 17:23:50 +00:00
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func ff_rgb24ToY_rvv, zve32x, zba
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-04 19:57:33 +00:00
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lw t1, 0(a5) # RY
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lw t3, 8(a5) # BY
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1:
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lw t2, 4(a5) # GY
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li t4, (32 << (15 - 1)) + (1 << (15 - 7))
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2:
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vsetvli t0, a4, e32, m8, ta, ma
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vlseg3e8.v v0, (a1)
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sub a4, a4, t0
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vzext.vf4 v8, v0
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sh1add t5, t0, t0 # t1 = 3 * t0
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vzext.vf4 v16, v2
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vzext.vf4 v24, v4
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add a1, t5, a1
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vmul.vx v8, v8, t1
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vmacc.vx v8, t2, v16
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vmacc.vx v8, t3, v24
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vadd.vx v8, v8, t4
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vsetvli zero, zero, e16, m4, ta, ma
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vnsra.wi v0, v8, 15 - 6
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vse16.v v0, (a0)
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sh1add a0, t0, a0
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bnez a4, 2b
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ret
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endfunc
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2024-06-05 15:36:42 +00:00
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func ff_bgr24ToUV_rvv, zve32x
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-05 15:36:42 +00:00
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lw t1, 20(a6) # BU
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lw t4, 32(a6) # BV
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lw t3, 12(a6) # RU
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lw t6, 24(a6) # RV
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j 1f
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endfunc
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2024-07-22 17:23:50 +00:00
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func ff_rgb24ToUV_rvv, zve32x, zba
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-05 15:36:42 +00:00
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lw t1, 12(a6) # RU
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lw t4, 24(a6) # RV
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lw t3, 20(a6) # BU
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lw t6, 32(a6) # BV
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1:
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lw t2, 16(a6) # GU
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lw t5, 28(a6) # GV
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li a7, (256 << (15 - 1)) + (1 << (15 - 7))
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2:
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vsetvli t0, a5, e32, m8, ta, ma
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vlseg3e8.v v0, (a3)
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sub a5, a5, t0
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vzext.vf4 v16, v0
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sh1add a6, t0, t0
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vzext.vf4 v24, v2
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vmul.vx v8, v16, t1
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add a3, a6, a3
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vmul.vx v16, v16, t4
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vmacc.vx v8, t2, v24
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vmacc.vx v16, t5, v24
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vzext.vf4 v24, v4
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vadd.vx v8, v8, a7
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vadd.vx v16, v16, a7
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vmacc.vx v8, t3, v24
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vmacc.vx v16, t6, v24
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vsetvli zero, zero, e16, m4, ta, ma
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vnsra.wi v0, v8, 15 - 6
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vnsra.wi v4, v16, 15 - 6
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vse16.v v0, (a0)
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sh1add a0, t0, a0
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vse16.v v4, (a1)
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sh1add a1, t0, a1
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bnez a5, 2b
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ret
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endfunc
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2024-06-05 16:32:31 +00:00
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func ff_bgr24ToUV_half_rvv, zve32x
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-05 16:32:31 +00:00
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lw t1, 20(a6) # BU
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lw t4, 32(a6) # BV
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lw t3, 12(a6) # RU
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lw t6, 24(a6) # RV
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j 1f
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endfunc
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2024-07-22 17:23:50 +00:00
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func ff_rgb24ToUV_half_rvv, zve32x, zba
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-05 16:32:31 +00:00
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lw t1, 12(a6) # RU
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lw t4, 24(a6) # RV
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lw t3, 20(a6) # BU
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lw t6, 32(a6) # BV
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1:
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lw t2, 16(a6) # GU
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lw t5, 28(a6) # GV
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li a7, (256 << 15) + (1 << (15 - 6))
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2:
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vsetvli t0, a5, e8, m1, ta, ma
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vlseg6e8.v v0, (a3)
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sh1add a6, t0, t0
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vwaddu.vv v8, v0, v3
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sub a5, a5, t0
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vwaddu.vv v10, v1, v4
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sh1add a3, a6, a3
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vwaddu.vv v12, v2, v5
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vsetvli zero, zero, e32, m4, ta, ma
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vzext.vf2 v20, v8
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vzext.vf2 v24, v10
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vzext.vf2 v28, v12
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vmul.vx v0, v20, t1
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vmul.vx v4, v20, t4
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vmacc.vx v0, t2, v24
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vmacc.vx v4, t5, v24
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vmacc.vx v0, t3, v28
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vmacc.vx v4, t6, v28
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vadd.vx v0, v0, a7
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vadd.vx v4, v4, a7
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vsetvli zero, zero, e16, m2, ta, ma
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vnsra.wi v0, v0, 15 - 5
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vnsra.wi v2, v4, 15 - 5
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vse16.v v0, (a0)
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sh1add a0, t0, a0
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vse16.v v2, (a1)
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sh1add a1, t0, a1
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bnez a5, 2b
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ret
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endfunc
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2024-06-06 14:49:21 +00:00
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.macro rgba_input chr0, chr1, high
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func ff_\chr1\()ToY_rvv, zve32x
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-06 14:49:21 +00:00
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lw t1, 8(a5) # BY
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lw t3, 0(a5) # RY
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j 1f
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endfunc
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2024-07-22 17:23:50 +00:00
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func ff_\chr0\()ToY_rvv, zve32x, zba
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-06 14:49:21 +00:00
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lw t1, 0(a5) # RY
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lw t3, 8(a5) # BY
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1:
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lw t2, 4(a5) # GY
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li t4, (32 << (15 - 1)) + (1 << (15 - 7))
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li t5, 0xff
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2:
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vsetvli t0, a4, e32, m8, ta, ma
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vle32.v v0, (a1)
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sub a4, a4, t0
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.if \high
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vsrl.vi v8, v0, 24
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.else
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vand.vx v8, v0, t5
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.endif
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sh2add a1, t0, a1
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vsrl.vi v16, v0, 8 * (1 + \high)
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vmul.vx v24, v8, t1
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vand.vx v16, v16, t5
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vsrl.vi v8, v0, 8 * (2 - \high)
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vmacc.vx v24, t2, v16
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vand.vx v8, v8, t5
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vadd.vx v24, v24, t4
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vmacc.vx v24, t3, v8
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vsetvli zero, zero, e16, m4, ta, ma
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vnsra.wi v0, v24, 15 - 6
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vse16.v v0, (a0)
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sh1add a0, t0, a0
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bnez a4, 2b
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ret
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endfunc
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2024-06-06 15:12:50 +00:00
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func ff_\chr1\()ToUV_rvv, zve32x
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-06 15:12:50 +00:00
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lw t1, 20(a6) # BU
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lw t4, 32(a6) # BV
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lw t3, 12(a6) # RU
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lw t6, 24(a6) # RV
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j 1f
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endfunc
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2024-07-22 17:23:50 +00:00
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func ff_\chr0\()ToUV_rvv, zve32x, zba
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-06 15:12:50 +00:00
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lw t1, 12(a6) # RU
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lw t4, 24(a6) # RV
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lw t3, 20(a6) # BU
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lw t6, 32(a6) # BV
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1:
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lw t2, 16(a6) # GU
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lw t5, 28(a6) # GV
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li a6, 0xff
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li a7, (256 << (15 - 1)) + (1 << (15 - 7))
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2:
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vsetvli t0, a5, e32, m8, ta, ma
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vle32.v v0, (a3)
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sub a5, a5, t0
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.if \high
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vsrl.vi v24, v0, 24
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.else
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vand.vx v24, v0, a6
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.endif
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sh2add a3, t0, a3
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vsrl.vi v8, v0, 8 * (1 + \high)
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vmul.vx v16, v24, t1
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vand.vx v8, v8, a6
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vmul.vx v24, v24, t4
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vmacc.vx v16, t2, v8
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vsrl.vi v0, v0, 8 * (2 - \high)
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vmacc.vx v24, t5, v8
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vand.vx v0, v0, a6
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vadd.vx v16, v16, a7
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vadd.vx v24, v24, a7
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vmacc.vx v16, t3, v0
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vmacc.vx v24, t6, v0
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vsetvli zero, zero, e16, m4, ta, ma
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vnsra.wi v0, v16, 15 - 6
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vnsra.wi v4, v24, 15 - 6
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vse16.v v0, (a0)
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sh1add a0, t0, a0
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vse16.v v4, (a1)
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sh1add a1, t0, a1
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bnez a5, 2b
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ret
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endfunc
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2024-06-06 18:15:08 +00:00
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func ff_\chr1\()ToUV_half_rvv, zve32x
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-06 18:15:08 +00:00
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lw t1, 20(a6) # BU
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lw t4, 32(a6) # BV
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lw t3, 12(a6) # RU
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lw t6, 24(a6) # RV
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j 1f
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endfunc
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2024-07-22 17:23:50 +00:00
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func ff_\chr0\()ToUV_half_rvv, zve32x, zba
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2024-07-22 19:17:40 +00:00
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lpad 0
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2024-06-06 18:15:08 +00:00
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lw t1, 12(a6) # RU
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lw t4, 24(a6) # RV
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lw t3, 20(a6) # BU
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lw t6, 32(a6) # BV
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1:
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lw t2, 16(a6) # GU
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lw t5, 28(a6) # GV
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li a6, 0xff
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li a7, (256 << 15) + (1 << (15 - 6))
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2:
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vsetvli t0, a5, e32, m4, ta, ma
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vlseg2e32.v v0, (a3)
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sub a5, a5, t0
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.if \high
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vsrl.vi v8, v0, 24
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vsrl.vi v12, v4, 24
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.else
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vand.vx v8, v0, a6
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vand.vx v12, v4, a6
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.endif
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sh3add a3, t0, a3
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vsrl.vi v16, v0, 8 * (1 + \high)
|
|
|
|
|
vsrl.vi v20, v4, 8 * (1 + \high)
|
|
|
|
|
vsrl.vi v24, v0, 8 * (2 - \high)
|
|
|
|
|
vsrl.vi v28, v4, 8 * (2 - \high)
|
|
|
|
|
vand.vx v16, v16, a6
|
|
|
|
|
vand.vx v20, v20, a6
|
|
|
|
|
vand.vx v24, v24, a6
|
|
|
|
|
vand.vx v28, v28, a6
|
|
|
|
|
vadd.vv v8, v8, v12
|
|
|
|
|
vadd.vv v16, v16, v20
|
|
|
|
|
vadd.vv v24, v24, v28
|
|
|
|
|
vmul.vx v0, v8, t1
|
|
|
|
|
vmul.vx v4, v8, t4
|
|
|
|
|
vmacc.vx v0, t2, v16
|
|
|
|
|
vmacc.vx v4, t5, v16
|
|
|
|
|
vmacc.vx v0, t3, v24
|
|
|
|
|
vmacc.vx v4, t6, v24
|
|
|
|
|
vadd.vx v0, v0, a7
|
|
|
|
|
vadd.vx v4, v4, a7
|
|
|
|
|
vsetvli zero, zero, e16, m2, ta, ma
|
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|
|
|
vnsra.wi v0, v0, 15 - 5
|
|
|
|
|
vnsra.wi v2, v4, 15 - 5
|
|
|
|
|
vse16.v v0, (a0)
|
|
|
|
|
sh1add a0, t0, a0
|
|
|
|
|
vse16.v v2, (a1)
|
|
|
|
|
sh1add a1, t0, a1
|
|
|
|
|
bnez a5, 2b
|
|
|
|
|
|
|
|
|
|
ret
|
|
|
|
|
endfunc
|
2024-06-06 14:49:21 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
rgba_input rgba32, bgra32, 0
|
|
|
|
|
rgba_input abgr32, argb32, 1
|
