2018-11-26 12:24:15 +00:00
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/*
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* AltiVec-enhanced yuv2yuvX
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*
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* Copyright (C) 2004 Romain Dolbeau <romain@dolbeau.org>
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* based on the equivalent C code in swscale.c
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2021-04-14 13:11:43 +00:00
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#include "libavutil/attributes.h"
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2020-06-10 13:38:08 +00:00
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#include "libavutil/mem_internal.h"
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libswscale/ppc: VSX-optimize 9-16 bit yuv2planeX
./ffmpeg_g -f rawvideo -pix_fmt rgb24 -s hd1080 -i /dev/zero -pix_fmt yuv420p16be \
-s 1920x1728 -f null -vframes 100 -v error -nostats -
9-14 bit funcs get about 6x speedup, 16-bit gets about 15x.
Fate passes, each format tested with an image to video conversion.
Only POWER8 includes 32-bit vector multiplies, so POWER7 is locked out
of the 16-bit function. This includes the vec_mulo/mule functions too,
not just vmuluwm.
With TIMER_REPORT skips disabled:
yuv420p9le
12412 UNITS in planarX, 131072 runs, 0 skips
73136 UNITS in planarX, 131072 runs, 0 skips
yuv420p9be
12481 UNITS in planarX, 131072 runs, 0 skips
73410 UNITS in planarX, 131072 runs, 0 skips
yuv420p10le
12322 UNITS in planarX, 131072 runs, 0 skips
72546 UNITS in planarX, 131072 runs, 0 skips
yuv420p10be
12291 UNITS in planarX, 131072 runs, 0 skips
72935 UNITS in planarX, 131072 runs, 0 skips
yuv420p12le
12316 UNITS in planarX, 131072 runs, 0 skips
72708 UNITS in planarX, 131072 runs, 0 skips
yuv420p12be
12319 UNITS in planarX, 131072 runs, 0 skips
72577 UNITS in planarX, 131072 runs, 0 skips
yuv420p14le
12259 UNITS in planarX, 131072 runs, 0 skips
72516 UNITS in planarX, 131072 runs, 0 skips
yuv420p14be
12440 UNITS in planarX, 131072 runs, 0 skips
72962 UNITS in planarX, 131072 runs, 0 skips
yuv420p16le
10548 UNITS in planarX, 131072 runs, 0 skips
73429 UNITS in planarX, 131072 runs, 0 skips
yuv420p16be
10634 UNITS in planarX, 131072 runs, 0 skips
150959 UNITS in planarX, 131072 runs, 0 skips
Signed-off-by: Lauri Kasanen <cand@gmx.com>
2019-01-13 08:26:20 +00:00
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static void FUNC(yuv2planeX_8_16)(const int16_t *filter, int filterSize,
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2018-11-26 12:24:15 +00:00
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const int16_t **src, uint8_t *dest,
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const uint8_t *dither, int offset, int x)
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{
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register int i, j;
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LOCAL_ALIGNED(16, int, val, [16]);
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vector signed int vo1, vo2, vo3, vo4;
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vector unsigned short vs1, vs2;
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vector unsigned char vf;
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vector unsigned int altivec_vectorShiftInt19 =
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vec_add(vec_splat_u32(10), vec_splat_u32(9));
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for (i = 0; i < 16; i++)
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val[i] = dither[(x + i + offset) & 7] << 12;
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vo1 = vec_ld(0, val);
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vo2 = vec_ld(16, val);
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vo3 = vec_ld(32, val);
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vo4 = vec_ld(48, val);
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for (j = 0; j < filterSize; j++) {
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unsigned int joffset=j<<1;
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unsigned int xoffset=x<<1;
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2019-03-18 11:24:42 +00:00
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vector unsigned char av_unused perm;
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2018-11-26 12:24:15 +00:00
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vector signed short l1,vLumFilter;
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LOAD_FILTER(vLumFilter,filter);
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vLumFilter = vec_splat(vLumFilter, 0);
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LOAD_L1(l1,src[j],perm);
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yuv2planeX_8(vo1, vo2, l1, src[j], x, perm, vLumFilter);
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yuv2planeX_8(vo3, vo4, l1, src[j], x + 8, perm, vLumFilter);
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}
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vo1 = vec_sra(vo1, altivec_vectorShiftInt19);
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vo2 = vec_sra(vo2, altivec_vectorShiftInt19);
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vo3 = vec_sra(vo3, altivec_vectorShiftInt19);
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vo4 = vec_sra(vo4, altivec_vectorShiftInt19);
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vs1 = vec_packsu(vo1, vo2);
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vs2 = vec_packsu(vo3, vo4);
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vf = vec_packsu(vs1, vs2);
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VEC_ST(vf, 0, dest);
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}
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static inline void yuv2planeX_u(const int16_t *filter, int filterSize,
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const int16_t **src, uint8_t *dest, int dstW,
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const uint8_t *dither, int offset, int x)
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{
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int i, j;
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for (i = x; i < dstW; i++) {
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int t = dither[(i + offset) & 7] << 12;
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for (j = 0; j < filterSize; j++)
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t += src[j][i] * filter[j];
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dest[i] = av_clip_uint8(t >> 19);
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}
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}
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static void FUNC(yuv2planeX)(const int16_t *filter, int filterSize,
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const int16_t **src, uint8_t *dest, int dstW,
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const uint8_t *dither, int offset)
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{
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int dst_u = -(uintptr_t)dest & 15;
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int i;
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yuv2planeX_u(filter, filterSize, src, dest, dst_u, dither, offset, 0);
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for (i = dst_u; i < dstW - 15; i += 16)
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libswscale/ppc: VSX-optimize 9-16 bit yuv2planeX
./ffmpeg_g -f rawvideo -pix_fmt rgb24 -s hd1080 -i /dev/zero -pix_fmt yuv420p16be \
-s 1920x1728 -f null -vframes 100 -v error -nostats -
9-14 bit funcs get about 6x speedup, 16-bit gets about 15x.
Fate passes, each format tested with an image to video conversion.
Only POWER8 includes 32-bit vector multiplies, so POWER7 is locked out
of the 16-bit function. This includes the vec_mulo/mule functions too,
not just vmuluwm.
With TIMER_REPORT skips disabled:
yuv420p9le
12412 UNITS in planarX, 131072 runs, 0 skips
73136 UNITS in planarX, 131072 runs, 0 skips
yuv420p9be
12481 UNITS in planarX, 131072 runs, 0 skips
73410 UNITS in planarX, 131072 runs, 0 skips
yuv420p10le
12322 UNITS in planarX, 131072 runs, 0 skips
72546 UNITS in planarX, 131072 runs, 0 skips
yuv420p10be
12291 UNITS in planarX, 131072 runs, 0 skips
72935 UNITS in planarX, 131072 runs, 0 skips
yuv420p12le
12316 UNITS in planarX, 131072 runs, 0 skips
72708 UNITS in planarX, 131072 runs, 0 skips
yuv420p12be
12319 UNITS in planarX, 131072 runs, 0 skips
72577 UNITS in planarX, 131072 runs, 0 skips
yuv420p14le
12259 UNITS in planarX, 131072 runs, 0 skips
72516 UNITS in planarX, 131072 runs, 0 skips
yuv420p14be
12440 UNITS in planarX, 131072 runs, 0 skips
72962 UNITS in planarX, 131072 runs, 0 skips
yuv420p16le
10548 UNITS in planarX, 131072 runs, 0 skips
73429 UNITS in planarX, 131072 runs, 0 skips
yuv420p16be
10634 UNITS in planarX, 131072 runs, 0 skips
150959 UNITS in planarX, 131072 runs, 0 skips
Signed-off-by: Lauri Kasanen <cand@gmx.com>
2019-01-13 08:26:20 +00:00
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FUNC(yuv2planeX_8_16)(filter, filterSize, src, dest + i, dither,
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2018-11-26 12:24:15 +00:00
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offset, i);
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yuv2planeX_u(filter, filterSize, src, dest, dstW, dither, offset, i);
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}
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static void FUNC(hScale_real)(SwsContext *c, int16_t *dst, int dstW,
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const uint8_t *src, const int16_t *filter,
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const int32_t *filterPos, int filterSize)
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{
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LOCAL_ALIGNED(16, int, tempo, [4]);
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2024-04-04 02:47:02 +00:00
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switch (filterSize) {
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case 4:
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for (register int i = 0; i < dstW; i++) {
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register int srcPos = filterPos[i];
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vector unsigned char src_vF = unaligned_load(srcPos, src);
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vector signed short src_v, filter_v;
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vector signed int val_vEven, val_s;
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src_v = // vec_unpackh sign-extends...
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(vector signed short)(VEC_MERGEH((vector unsigned char)vzero, src_vF));
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// now put our elements in the even slots
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src_v = vec_mergeh(src_v, (vector signed short)vzero);
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GET_VF4(i, filter_v, filter);
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val_vEven = vec_mule(src_v, filter_v);
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val_s = vec_sums(val_vEven, vzero);
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vec_st(val_s, 0, tempo);
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dst[i] = FFMIN(tempo[3] >> 7, (1 << 15) - 1);
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}
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2018-11-26 12:24:15 +00:00
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break;
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2024-04-04 02:47:02 +00:00
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case 8:
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for (register int i = 0; i < dstW; i++) {
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register int srcPos = filterPos[i];
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vector unsigned char src_vF, av_unused src_v0, av_unused src_v1;
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vector unsigned char av_unused permS;
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vector signed short src_v, filter_v;
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vector signed int val_v, val_s;
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FIRST_LOAD(src_v0, srcPos, src, permS);
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LOAD_SRCV8(srcPos, 0, src, permS, src_v0, src_v1, src_vF);
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src_v = // vec_unpackh sign-extends...
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(vector signed short)(VEC_MERGEH((vector unsigned char)vzero, src_vF));
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filter_v = vec_ld(i << 4, filter);
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val_v = vec_msums(src_v, filter_v, (vector signed int)vzero);
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val_s = vec_sums(val_v, vzero);
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vec_st(val_s, 0, tempo);
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dst[i] = FFMIN(tempo[3] >> 7, (1 << 15) - 1);
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}
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2018-11-26 12:24:15 +00:00
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break;
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2024-04-04 02:47:02 +00:00
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case 16:
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for (register int i = 0; i < dstW; i++) {
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register int srcPos = filterPos[i];
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2018-11-26 12:24:15 +00:00
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2024-04-04 02:47:02 +00:00
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vector unsigned char src_vF = unaligned_load(srcPos, src);
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vector signed short src_vA = // vec_unpackh sign-extends...
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(vector signed short)(VEC_MERGEH((vector unsigned char)vzero, src_vF));
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vector signed short src_vB = // vec_unpackh sign-extends...
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(vector signed short)(VEC_MERGEL((vector unsigned char)vzero, src_vF));
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vector signed short filter_v0 = vec_ld(i << 5, filter);
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vector signed short filter_v1 = vec_ld((i << 5) + 16, filter);
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2018-11-26 12:24:15 +00:00
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2024-04-04 02:47:02 +00:00
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vector signed int val_acc = vec_msums(src_vA, filter_v0, (vector signed int)vzero);
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vector signed int val_v = vec_msums(src_vB, filter_v1, val_acc);
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2018-11-26 12:24:15 +00:00
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2024-04-04 02:47:02 +00:00
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vector signed int val_s = vec_sums(val_v, vzero);
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2018-11-26 12:24:15 +00:00
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2024-04-04 02:47:02 +00:00
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VEC_ST(val_s, 0, tempo);
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dst[i] = FFMIN(tempo[3] >> 7, (1 << 15) - 1);
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}
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2018-11-26 12:24:15 +00:00
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break;
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2024-04-04 02:47:02 +00:00
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default:
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2024-04-04 02:43:38 +00:00
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for (register int i = 0; i < dstW; i++) {
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register int j;
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register int srcPos = filterPos[i];
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register int val = 0;
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for (j = 0; j < filterSize; j++)
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val += ((int)src[srcPos + j]) * filter[filterSize * i + j];
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dst[i] = FFMIN(val >> 7, (1 << 15) - 1);
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}
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break;
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2024-04-04 02:47:02 +00:00
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}
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2018-11-26 12:24:15 +00:00
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}
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