2022-09-26 14:52:46 +00:00
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/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_ps_add_squares_rvv, zve32f
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1:
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vsetvli t0, a2, e32, m1, ta, ma
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vlseg2e32.v v24, (a1)
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sub a2, a2, t0
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vle32.v v16, (a0)
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sh3add a1, t0, a1
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vfmacc.vv v16, v24, v24
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vfmacc.vv v16, v25, v25
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vse32.v v16, (a0)
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sh2add a0, t0, a0
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bnez a2, 1b
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ret
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endfunc
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2022-09-26 14:52:47 +00:00
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func ff_ps_mul_pair_single_rvv, zve32f
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1:
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vsetvli t0, a3, e32, m1, ta, ma
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vlseg2e32.v v24, (a1)
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sub a3, a3, t0
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vle32.v v16, (a2)
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sh3add a1, t0, a1
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vfmul.vv v24, v24, v16
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sh2add a2, t0, a2
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vfmul.vv v25, v25, v16
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vsseg2e32.v v24, (a0)
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sh3add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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2022-09-26 14:52:48 +00:00
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func ff_ps_hybrid_analysis_rvv, zve32f
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/* We need 26 FP registers, for 20 scratch ones. Spill fs0-fs5. */
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addi sp, sp, -32
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.irp n, 0, 1, 2, 3, 4, 5
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fsw fs\n, (4 * \n)(sp)
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.endr
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.macro input, j, fd0, fd1, fd2, fd3
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flw \fd0, (4 * ((\j * 2) + 0))(a1)
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flw fs4, (4 * (((12 - \j) * 2) + 0))(a1)
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flw \fd1, (4 * ((\j * 2) + 1))(a1)
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fsub.s \fd3, \fd0, fs4
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flw fs5, (4 * (((12 - \j) * 2) + 1))(a1)
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fadd.s \fd2, \fd1, fs5
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fadd.s \fd0, \fd0, fs4
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fsub.s \fd1, \fd1, fs5
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.endm
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// re0, re1, im0, im1
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input 0, ft0, ft1, ft2, ft3
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input 1, ft4, ft5, ft6, ft7
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input 2, ft8, ft9, ft10, ft11
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input 3, fa0, fa1, fa2, fa3
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input 4, fa4, fa5, fa6, fa7
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input 5, fs0, fs1, fs2, fs3
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flw fs4, (4 * ((6 * 2) + 0))(a1)
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flw fs5, (4 * ((6 * 2) + 1))(a1)
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add a2, a2, 6 * 2 * 4 // point to filter[i][6][0]
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li t4, 8 * 2 * 4 // filter byte stride
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slli a3, a3, 3 // output byte stride
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1:
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.macro filter, vs0, vs1, fo0, fo1, fo2, fo3
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vfmacc.vf v8, \fo0, \vs0
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vfmacc.vf v9, \fo2, \vs0
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vfnmsac.vf v8, \fo1, \vs1
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vfmacc.vf v9, \fo3, \vs1
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.endm
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vsetvli t0, a4, e32, m1, ta, ma
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/*
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* The filter (a2) has 16 segments, of which 13 need to be extracted.
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* R-V V supports only up to 8 segments, so unrolling is unavoidable.
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*/
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addi t1, a2, -48
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vlse32.v v22, (a2), t4
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addi t2, a2, -44
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vlse32.v v16, (t1), t4
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addi t1, a2, -40
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vfmul.vf v8, v22, fs4
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vlse32.v v24, (t2), t4
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addi t2, a2, -36
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vfmul.vf v9, v22, fs5
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vlse32.v v17, (t1), t4
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addi t1, a2, -32
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vlse32.v v25, (t2), t4
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addi t2, a2, -28
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filter v16, v24, ft0, ft1, ft2, ft3
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vlse32.v v18, (t1), t4
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addi t1, a2, -24
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vlse32.v v26, (t2), t4
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addi t2, a2, -20
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filter v17, v25, ft4, ft5, ft6, ft7
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vlse32.v v19, (t1), t4
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addi t1, a2, -16
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vlse32.v v27, (t2), t4
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addi t2, a2, -12
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filter v18, v26, ft8, ft9, ft10, ft11
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vlse32.v v20, (t1), t4
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addi t1, a2, -8
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vlse32.v v28, (t2), t4
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addi t2, a2, -4
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filter v19, v27, fa0, fa1, fa2, fa3
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vlse32.v v21, (t1), t4
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sub a4, a4, t0
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vlse32.v v29, (t2), t4
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slli t1, t0, 3 + 1 + 2 // ctz(8 * 2 * 4)
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add a2, a2, t1
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filter v20, v28, fa4, fa5, fa6, fa7
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filter v21, v29, fs0, fs1, fs2, fs3
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add t2, a0, 4
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vsse32.v v8, (a0), a3
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mul t0, t0, a3
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vsse32.v v9, (t2), a3
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add a0, a0, t0
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bnez a4, 1b
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.irp n, 5, 4, 3, 2, 1, 0
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flw fs\n, (4 * \n)(sp)
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.endr
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addi sp, sp, 32
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ret
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.purgem input
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.purgem filter
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endfunc
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2022-09-26 14:52:49 +00:00
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func ff_ps_hybrid_analysis_ileave_rvv, zve32x /* no needs for zve32f here */
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slli t0, a2, 5 + 1 + 2 // ctz(32 * 2 * 4)
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sh2add a1, a2, a1
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add a0, a0, t0
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addi a2, a2, -64
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li t1, 38 * 64 * 4
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li t6, 64 * 4 // (uint8_t *)L[x][j+1][i] - L[x][j][i]
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add a4, a1, t1 // &L[1]
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beqz a2, 3f
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1:
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mv t0, a0
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mv t1, a1
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mv t3, a3
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mv t4, a4
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addi a2, a2, 1
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2:
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vsetvli t5, t3, e32, m1, ta, ma
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vlse32.v v16, (t1), t6
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sub t3, t3, t5
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vlse32.v v17, (t4), t6
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mul t2, t5, t6
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vsseg2e32.v v16, (t0)
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sh3add t0, t5, t0
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add t1, t1, t2
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add t4, t4, t2
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bnez t3, 2b
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add a0, a0, 32 * 2 * 4
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add a1, a1, 4
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add a4, a4, 4
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bnez a2, 1b
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3:
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ret
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endfunc
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2022-09-26 14:52:50 +00:00
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func ff_ps_hybrid_synthesis_deint_rvv, zve32x
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slli t1, a2, 5 + 1 + 2
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sh2add a0, a2, a0
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add a1, a1, t1
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addi a2, a2, -64
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li t1, 38 * 64 * 4
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li t6, 64 * 4
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add a4, a0, t1
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beqz a2, 3f
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1:
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mv t0, a0
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mv t1, a1
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mv t3, a3
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mv t4, a4
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addi a2, a2, 1
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2:
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vsetvli t5, t3, e32, m1, ta, ma
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vlseg2e32.v v16, (t1)
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sub t3, t3, t5
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vsse32.v v16, (t0), t6
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mul t2, t5, t6
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vsse32.v v17, (t4), t6
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sh3add t1, t5, t1
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add t0, t0, t2
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add t4, t4, t2
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bnez t3, 2b
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add a0, a0, 4
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add a1, a1, 32 * 2 * 4
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add a4, a4, 4
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bnez a2, 1b
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3:
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ret
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endfunc
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2022-09-26 14:52:51 +00:00
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func ff_ps_stereo_interpolate_rvv, zve32f
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vsetvli t0, zero, e32, m1, ta, ma
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vid.v v24
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flw ft0, (a2)
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vadd.vi v24, v24, 1 // v24[i] = i + 1
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flw ft1, 4(a2)
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vfcvt.f.xu.v v24, v24
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flw ft2, 8(a2)
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vfmv.v.f v16, ft0
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flw ft3, 12(a2)
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vfmv.v.f v17, ft1
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flw ft0, (a3)
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vfmv.v.f v18, ft2
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flw ft1, 4(a3)
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vfmv.v.f v19, ft3
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flw ft2, 8(a3)
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vfmv.v.f v20, ft0
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flw ft3, 12(a3)
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vfmv.v.f v21, ft1
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fcvt.s.wu ft4, t0 // (float)(vlenb / sizeof (float))
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vfmv.v.f v22, ft2
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fmul.s ft0, ft0, ft4
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vfmv.v.f v23, ft3
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fmul.s ft1, ft1, ft4
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vfmacc.vv v16, v24, v20 // h0 += (i + 1) * h0_step
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fmul.s ft2, ft2, ft4
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vfmacc.vv v17, v24, v21
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fmul.s ft3, ft3, ft4
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vfmacc.vv v18, v24, v22
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vfmacc.vv v19, v24, v23
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1:
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vsetvli t0, a4, e32, m1, ta, ma
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vlseg2e32.v v8, (a0) // v8:l_re, v9:l_im
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sub a4, a4, t0
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vlseg2e32.v v10, (a1) // v10:r_re, v11:r_im
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vfmul.vv v12, v8, v16
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vfmul.vv v13, v9, v16
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vfmul.vv v14, v8, v17
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vfmul.vv v15, v9, v17
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vfmacc.vv v12, v10, v18
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vfmacc.vv v13, v11, v18
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vfmacc.vv v14, v10, v19
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vfmacc.vv v15, v11, v19
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vsseg2e32.v v12, (a0)
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sh3add a0, t0, a0
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vsseg2e32.v v14, (a1)
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sh3add a1, t0, a1
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vfadd.vf v16, v16, ft0 // h0 += (vlenb / sizeof (float)) * h0_step
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vfadd.vf v17, v17, ft1
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vfadd.vf v18, v18, ft2
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vfadd.vf v19, v19, ft3
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bnez a4, 1b
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ret
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endfunc
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