RepoMirrors/crash
1
0
Fork 0
mirror of https://github.com/crash-utility/crash synced 2025-02-23 00:46:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

xen: increase __PHYSICAL_MASK_SHIFT_XEN to 52

Browse Source 
The current value of __PHYSICAL_MASK_SHIFT_XEN in crash (40) is
smaller than the kernel (52) since kernel commit 6f0e8bf167 (xen:
support 52 bit physical addresses in pv guests).

This can cause x86_64_pud_offset() to lose the most significant
bits of pgd_pte, leading to a failed xen_m2p() translation,
resulting in crash failing with an error message like this:
   crash: read error: physical address: ffffffffffffffff  type: "pud page"

Both Intel and AMD documentation mandate that unused physical
address bits must be 0, so there is no need to explicitly mask them
out with a mask narrower than the architecture limit of 52. This
is also confirmed by this kernel commit: b83ce5ee91.

Increase the value of __PHYSICAL_MASK_SHIFT_XEN to 52.

Signed-off-by: Jiri Bohac <jbohac@suse.cz>
This commit is contained in:
Jiri Bohac 2021-01-25 22:44:50 +01:00 committed by Kazuhito Hagio
parent 33c322e929
commit fdb41f0b6f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
defs.h
View File

@ -3585,7 +3585,7 @@ struct arm64_stackframe {
* PHYSICAL_PAGE_MASK changed (enlarged) between 2.4 and 2.6, so
* for safety, use the 2.6 values to generate it.
*/
#define __PHYSICAL_MASK_SHIFT_XEN 40
#define __PHYSICAL_MASK_SHIFT_XEN 52
#define __PHYSICAL_MASK_SHIFT_2_6 46
#define __PHYSICAL_MASK_SHIFT_5LEVEL 52
#define __PHYSICAL_MASK_SHIFT (machdep->machspec->physical_mask_shift)