Commit Graph

12 Commits

Author SHA1 Message Date
Boris Ranto
2172dfb594 Fix ppc64 support for ceph
The ppc64 support requires a couple of changes:
- adding the ppc64 support to cmake
- changing optimized crc32 code to compile on ppc64le only
- moving ifdef condition before crc32_align to avoid defined but not
used warning

Signed-off-by: Boris Ranto <branto@redhat.com>
2017-08-04 10:56:03 +02:00
James Page
5d92c79b8e build: misc fixes for cmake build on i386
Scope SIMD CPU flag detection base on target architecture,
resolving build failures in gf-complete on i386; this is
inline with the previous autotools based feature detection.

Only compile crypto/isa-l if yasm 64 bit complier is found,
effectively limiting scope to x86_64.

Signed-off-by: James Page <james.page@ubuntu.com>
2017-06-06 16:34:50 +01:00
Kefu Chai
195425c9ca cmake: extract ppc64le detection into SIMDExt.cmake
Signed-off-by: Kefu Chai <kchai@redhat.com>
2017-04-03 01:44:17 +08:00
Dan Mick
ac4815f74b cmake/modules/SIMDExt.cmake: armv8 crypto intrinsics
Test not only for -march support, but also the actual
presence of the intrinsic routines.  Not sure why, but gcc
4.8.5 passes the first but not the second.

Fixes: http://tracker.ceph.com/issues/19386
Signed-off-by: Dan Mick <dan.mick@redhat.com>
2017-03-27 09:35:22 -07:00
Dan Mick
ef8980bad2 cmake/modules/SIMDExt.cmake: add whitespace
readability, man, readability

Signed-off-by: Dan Mick <dan.mick@redhat.com>
2017-03-24 20:10:15 -07:00
wei xiao
b0ae5ae2ad crc32c: optimize aarch64 crc32c implementation
ARMv8 defines PMULL crypto instruction.
This patch optimizes crc32c calculate with the instruction when
available rather than original linear crc instructions.

ceph crc32c performance unit test shows that the optimization get
~ x3.90 speedups on ThunderX ARM Core@2.0GHz (Cavium)
~ x1.45 speedups on ARM Cortex-A57@2.1GHz (Huaiwei)
~ x1.16 speedups on ARM Cortex-A57@2.0GHz (Softiron)

Jira: ENTLLT-358
Change-Id: I657422cd20c9ca78237cd060210a5383f4122575
Signed-off-by: wei xiao <wei.xiao@linaro.org>
2017-02-04 06:20:50 +00:00
Alexander Graf
e70ab48b7f AArch64: Detect crc32 extension support from assembler
The used compiler may or may not be recent enough to recognize the
crc32 extended cpu type. However, it does not really have to know about
them either, since all we do is pass inline assembly instructions to
the assembler.

This patch moves the crc cpu extension detection from compiler based
to assembler based, so that we can build optimized code even when the
compiler does not know about the cpu type yet.

Fixes: http://tracker.ceph.com/issues/17516
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-10-10 14:51:44 +02:00
Bassam Tabbara
e7e0b1bc1e erasure-code: Backward compatibility with legacy EC plugins
Resurrected jerasure_generic, jerasure_sse3, jerasure_sse4, jerasure_neon,
shec_generic, shec_sse3, shec_sse4 and shec_neon. These all are exact
copies of the new jerasure and shec plugins that support SIMD detection.

Moved EC preload code in ceph-mon and ceph-osd to a central location, added
warning when preloading legacy plugins.

OSMonitor::get_erasure_code and OSDMonitor:normalize_profile will now check
if legacy EC plugins are used and log a warning.

Added tests to check that warnings make it to the log.

Signed-off-by: Bassam Tabbara <bassam.tabbara@quantum.com>
2016-09-29 10:34:34 -07:00
Bassam Tabbara
10d06eb115 cmake: normalize use of SIMD flags
Signed-off-by: Bassam Tabbara <bassam.tabbara@quantum.com>
2016-09-29 10:34:33 -07:00
Bassam Tabbara
cc62c11a76 erasure-code: Remove SIMD flavors for jerasure and shec
By switching to a new gf-complete with SIMD runtime detection, we can now remove all the different flavors of jerasure and shec. This simplifies deployment and configuration of erasure coding, enables hetergenous OSDs, and enables us to take advantage of new performance improvements in jerasure without config/build changes.

This commit removes flavors from cmake, removes ErasureCodePluginSelect___, and fixes unit tests. There is now a single plugin for jerasure and a single plugin for shec.

SIMDExt.cmake was changed so that its a little more generic, and is not polluted with gf-complete specific CFLAG defines. The #define for SIMD instruction were based on gf-complete.

I also added a small init helper for jerasure that has code that was common between jerasure and shec.

Signed-off-by: Bassam Tabbara <bassam.tabbara@quantum.com>
2016-09-29 10:34:33 -07:00
Dan Mick
3fdccc9e2b Set ARM_CRC_FLAGS from the CRC test rather than ARM_NEON_FLAGS
Fixes: http://tracker.ceph.com/issues/17250
Signed-off-by: Dan Mick <dan.mick@redhat.com>
2016-09-08 20:28:55 -07:00
Kefu Chai
367755e7f7 cmake: pass -DINTEL* to gf-complete cflags
* in addition to the -march=foobar, we also need to pass -DFOOBAR to
  gf-complete sources' cflags, so that the SIMD instructions can be
  generated as expected.
* also extract the compiler support for instruction extensions detections
  into SIMDExt.cmake.
* and only check the compiler support if CMAKE_SYSTEM_PROCESSOR matches
  with the instruction-set/arch to be checked.

Signed-off-by: tone.zhang <tone.zhang@linaro.org>
Signed-off-by: Kefu Chai <kchai@redhat.com>
2016-09-02 16:23:54 +08:00