mirror of
https://github.com/dense-analysis/ale
synced 2024-12-21 13:51:51 +00:00
b8bf7b220d
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
27 lines
599 B
Plaintext
27 lines
599 B
Plaintext
Before:
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runtime ale_linters/vhdl/ghdl.vim
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After:
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call ale#linter#Reset()
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Execute(The ghdl handler should parse lines correctly):
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AssertEqual
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\ [
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\ {
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\ 'lnum': 41,
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\ 'col' : 5,
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\ 'type': 'E',
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\ 'text': "error: 'begin' is expected instead of 'if'"
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\ },
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\ {
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\ 'lnum': 12,
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\ 'col' : 8,
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\ 'type': 'E',
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\ 'text': ' no declaration for "i0"'
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\ },
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\ ],
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\ ale_linters#vhdl#ghdl#Handle(bufnr(''), [
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\ "dff_en.vhd:41:5:error: 'begin' is expected instead of 'if'",
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\ '/path/to/file.vhdl:12:8: no declaration for "i0"',
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\ ])
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