mirror of
https://github.com/dense-analysis/ale
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b8bf7b220d
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
38 lines
1.3 KiB
VimL
38 lines
1.3 KiB
VimL
" Author: John Gentile <johncgentile17@gmail.com>
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" Description: Adds support for Xilinx Vivado `xvhdl` VHDL compiler/checker
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call ale#Set('vhdl_xvhdl_executable', 'xvhdl')
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" Use VHDL-2008. See `$ xvhdl -h` for more options
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call ale#Set('vhdl_xvhdl_options', '--2008')
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function! ale_linters#vhdl#xvhdl#GetCommand(buffer) abort
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return '%e ' . ale#Pad(ale#Var(a:buffer, 'vhdl_xvhdl_options')) . ' %t'
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endfunction
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function! ale_linters#vhdl#xvhdl#Handle(buffer, lines) abort
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"Matches patterns like the following:
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" ERROR: [VRFC 10-91] aresetn is not declared [/path/to/file.vhd:17]
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" ERROR: [VRFC 10-91] m_axis_tx_tdata is not declared [/home/user/tx_data.vhd:128]
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let l:pattern = '^ERROR:\s\+\(\[.*\)\[.*:\([0-9]\+\)\]'
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let l:output = []
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" NOTE: `xvhdl` only prints 'INFO' and 'ERROR' messages
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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call add(l:output, {
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\ 'lnum': l:match[2] + 0,
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\ 'type': 'E',
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\ 'text': l:match[1],
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('vhdl', {
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\ 'name': 'xvhdl',
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\ 'output_stream': 'stdout',
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\ 'executable_callback': ale#VarFunc('vhdl_xvhdl_executable'),
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\ 'command_callback': 'ale_linters#vhdl#xvhdl#GetCommand',
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\ 'callback': 'ale_linters#vhdl#xvhdl#Handle',
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\})
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