mirror of https://github.com/dense-analysis/ale
119 lines
4.4 KiB
Plaintext
119 lines
4.4 KiB
Plaintext
===============================================================================
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ALE Verilog/SystemVerilog Integration *ale-verilog-options*
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===============================================================================
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ALE can use five different linters for Verilog HDL:
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HDL Checker
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Using `hdl_checker --lsp`
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iverilog:
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Using `iverilog -t null -Wall`
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verilator
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Using `verilator --lint-only -Wall`
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ModelSim/Questa
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Using `vlog -quiet -lint`
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Vivado
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Using `xvlog`
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By default, both 'verilog' and 'systemverilog' filetypes are checked.
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You can limit 'systemverilog' files to be checked using only 'verilator' by
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defining 'g:ale_linters' variable:
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>
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au FileType systemverilog
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\ let g:ale_linters = {'systemverilog' : ['verilator'],}
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<
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===============================================================================
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General notes
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Linters/compilers that utilize a "work" directory for analyzing designs- such
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as ModelSim and Vivado- can be passed the location of these directories as
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part of their respective option strings listed below. This is useful for
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holistic analysis of a file (e.g. a design with components, packages, or other
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code defined external to the current file as part of a larger project) or
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when wanting to simply pass an alternative location for the auto-generated
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work directories (such as '/tmp') so as to not muddle the current directory.
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Since these type of linters often use this work directory for holding compiled
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design data as part of a single build process, they sometimes cannot handle
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the frequent, asynchronous application launches when linting while text is
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changing. This can happen in the form of hangs or crashes. To help prevent
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this when using these linters, it may help to run linting less frequently; for
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example, only when a file is saved.
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HDL Checker is an alternative for some of the issues described above. It wraps
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around ghdl, Vivado and ModelSim/Questa and, when using the latter, it can
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handle mixed language (VHDL, Verilog, SystemVerilog) designs.
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===============================================================================
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hdl-checker *ale-verilog-hdl-checker*
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See |ale-vhdl-hdl-checker|
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===============================================================================
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iverilog *ale-verilog-iverilog*
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No additional options
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===============================================================================
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verilator *ale-verilog-verilator*
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g:ale_verilog_verilator_options *g:ale_verilog_verilator_options*
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*b:ale_verilog_verilator_options*
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Type: |String|
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Default: `''`
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This variable can be changed to modify 'verilator' command arguments
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For example `'-sv --default-language "1800-2012"'` if you want to enable
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SystemVerilog parsing and select the 2012 version of the language.
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===============================================================================
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vlog *ale-verilog-vlog*
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g:ale_verilog_vlog_executable *g:ale_verilog_vlog_executable*
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*b:ale_verilog_vlog_executable*
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Type: |String|
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Default: `'vlog'`
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This variable can be changed to the path to the 'vlog' executable.
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g:ale_verilog_vlog_options *g:ale_verilog_vlog_options*
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*b:ale_verilog_vlog_options*
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Type: |String|
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Default: `'-quiet -lint'`
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This variable can be changed to modify the flags/options passed to 'vlog'.
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===============================================================================
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xvlog *ale-verilog-xvlog*
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g:ale_verilog_xvlog_executable *g:ale_verilog_xvlog_executable*
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*b:ale_verilog_xvlog_executable*
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Type: |String|
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Default: `'xvlog'`
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This variable can be changed to the path to the 'xvlog' executable.
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g:ale_verilog_xvlog_options *g:ale_verilog_xvlog_options*
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*b:ale_verilog_xvlog_options*
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Type: |String|
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Default: `''`
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This variable can be changed to modify the flags/options passed to 'xvlog'.
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===============================================================================
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vim:tw=78:ts=2:sts=2:sw=2:ft=help:norl:
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