mirror of
https://github.com/dense-analysis/ale
synced 2024-12-27 16:42:19 +00:00
b8bf7b220d
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
25 lines
626 B
Plaintext
25 lines
626 B
Plaintext
Before:
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runtime ale_linters/verilog/vlog.vim
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After:
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call ale#linter#Reset()
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Execute(The vlog handler should parse lines correctly):
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AssertEqual
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\ [
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\ {
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\ 'lnum': 7,
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\ 'type': 'W',
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\ 'text': '(vlog-2623) Undefined variable: C.'
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\ },
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\ {
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\ 'lnum': 1,
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\ 'type': 'E',
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\ 'text': '(vlog-13294) Identifier must be declared with a port mode: C.'
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\ },
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\ ],
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\ ale_linters#verilog#vlog#Handle(bufnr(''), [
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\ '** Warning: add.v(7): (vlog-2623) Undefined variable: C.',
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\ '** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.',
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\ ])
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