mirror of
https://github.com/dense-analysis/ale
synced 2024-12-19 21:02:02 +00:00
b8bf7b220d
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
19 lines
416 B
Plaintext
19 lines
416 B
Plaintext
Before:
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runtime ale_linters/verilog/xvlog.vim
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After:
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call ale#linter#Reset()
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Execute(The xvlog handler should parse lines correctly):
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AssertEqual
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\ [
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\ {
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\ 'lnum': 5,
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\ 'type': 'E',
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\ 'text': '[VRFC 10-1412] syntax error near output '
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\ },
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\ ],
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\ ale_linters#verilog#xvlog#Handle(bufnr(''), [
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\ 'ERROR: [VRFC 10-1412] syntax error near output [/path/to/file.v:5]',
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\ ])
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