3 Commits

Author	SHA1	Message	Date
John Gentile	b8bf7b220d	Add VHDL Support & Newer Verilog Linters (#2229) ... * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters	2019-01-27 09:46:33 +00:00
w0rp	fdc7166c3c	Use equal signs for language documentation sections	2017-07-08 14:17:26 +01:00
Tarik Graba	01ecf2a75f	Adds an option to pass additional arguments to the verilog/verilator … (#698) ... * Adds an option to pass additional arguments to the verilog/verilator linter The new otion is g:ale_verilog_verilator_options + doc * Spell check verilog linter doc file * Add entries to the verilog linters in the doc table of content * Vader test for verilog/verilator linter args option verilog_verilator_options	2017-06-29 09:15:52 +01:00