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ale/ale_linters/verilog/vlog.vim

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Add VHDL Support & Newer Verilog Linters (#2229) * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
2019-01-27 09:46:33 +00:00
" Author: John Gentile <johncgentile17@gmail.com>
" Description: Adds support for Mentor Graphics Questa/ModelSim `vlog` Verilog compiler/checker
call ale#Set('verilog_vlog_executable', 'vlog')
" See `$ vlog -h` for more options
call ale#Set('verilog_vlog_options', '-quiet -lint')
function! ale_linters#verilog#vlog#GetCommand(buffer) abort
return '%e ' . ale#Pad(ale#Var(a:buffer, 'verilog_vlog_options')) . ' %t'
endfunction
function! ale_linters#verilog#vlog#Handle(buffer, lines) abort
"Matches patterns like the following:
"** Warning: add.v(7): (vlog-2623) Undefined variable: C.
"** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.
verilog: Add filename to vlog linter output
2019-12-05 18:35:34 +00:00
let l:pattern = '^**\s\(\w*\): \([a-zA-Z0-9\-\.\_\/ ]\+\)(\(\d\+\)):\s\+\(.*\)'
Add VHDL Support & Newer Verilog Linters (#2229) * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
2019-01-27 09:46:33 +00:00
let l:output = []
for l:match in ale#util#GetMatches(a:lines, l:pattern)
Update syntax checking * Line continuation characters should be on the same lines. * .vim file line indentation should be a multiple of 4.
2019-02-06 18:05:13 +00:00
call add(l:output, {
verilog: Add filename to vlog linter output
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\ 'lnum': l:match[3] + 0,
Update syntax checking * Line continuation characters should be on the same lines. * .vim file line indentation should be a multiple of 4.
2019-02-06 18:05:13 +00:00
\ 'type': l:match[1] is? 'Error' ? 'E' : 'W',
verilog: Add filename to vlog linter output
2019-12-05 18:35:34 +00:00
\ 'text': l:match[4],
\ 'filename': l:match[2],
Update syntax checking * Line continuation characters should be on the same lines. * .vim file line indentation should be a multiple of 4.
2019-02-06 18:05:13 +00:00
\})
Add VHDL Support & Newer Verilog Linters (#2229) * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
2019-01-27 09:46:33 +00:00
endfor
Update vlog parser to handle new output format Re #2812, the parser now takes a second pass through the output using an updated regex.
2019-10-05 17:44:02 +00:00
"Matches patterns like the following:
"** Warning: (vlog-2623) add.v(7): Undefined variable: C.
"** Error: (vlog-13294) file.v(1): Identifier must be declared with a port mode: C.
" let l:pattern = '^**\s\(\w*\):[a-zA-Z0-9\-\.\_\/ ]\+(\(\d\+\)):\s\+\(.*\)'
verilog: Add filename to vlog linter output
2019-12-05 18:35:34 +00:00
let l:pattern = '^**\s\(\w*\):\s\([^)]*)\) \([a-zA-Z0-9\-\.\_\/ ]\+\)(\(\d\+\)):\s\+\(.*\)'
Update vlog parser to handle new output format Re #2812, the parser now takes a second pass through the output using an updated regex.
2019-10-05 17:44:02 +00:00
for l:match in ale#util#GetMatches(a:lines, l:pattern)
call add(l:output, {
verilog: Add filename to vlog linter output
2019-12-05 18:35:34 +00:00
\ 'lnum': l:match[4] + 0,
Update vlog parser to handle new output format Re #2812, the parser now takes a second pass through the output using an updated regex.
2019-10-05 17:44:02 +00:00
\ 'type': l:match[1] is? 'Error' ? 'E' : 'W',
verilog: Add filename to vlog linter output
2019-12-05 18:35:34 +00:00
\ 'text': l:match[2] . ' ' . l:match[5],
\ 'filename': l:match[3],
Update vlog parser to handle new output format Re #2812, the parser now takes a second pass through the output using an updated regex.
2019-10-05 17:44:02 +00:00
\})
endfor
Add VHDL Support & Newer Verilog Linters (#2229) * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
2019-01-27 09:46:33 +00:00
return l:output
endfunction
call ale#linter#Define('verilog', {
\ 'name': 'vlog',
\ 'output_stream': 'stdout',
#2132 - Replace all uses of foo_callback with foo
2019-02-22 18:05:04 +00:00
\ 'executable': {b -> ale#Var(b, 'verilog_vlog_executable')},
\ 'command': function('ale_linters#verilog#vlog#GetCommand'),
Add VHDL Support & Newer Verilog Linters (#2229) * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
2019-01-27 09:46:33 +00:00
\ 'callback': 'ale_linters#verilog#vlog#Handle',
\})