mirror of https://github.com/mpv-player/mpv
Various improvement, fix build on AMD-64 and icc
Original Thred: Date: Apr 25, 2006 2:23 PM Subject: Re: [MPlayer-dev-eng] Re: [PATCH] Various improvement in TOOLS/cpuinfo.c git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@18512 b3059339-0415-0410-9bf9-f77b7e298cf2
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gpoirier
parent
2899c32f78
commit
fa6d253ddb
104
TOOLS/cpuinfo.c
104
TOOLS/cpuinfo.c
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@ -6,6 +6,7 @@
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#include <sys/time.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#ifdef __MINGW32__
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#include <sys/timeb.h>
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@ -42,13 +43,9 @@ static cpuid_regs_t
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cpuid(int func) {
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cpuid_regs_t regs;
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#define CPUID ".byte 0x0f, 0xa2; "
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asm("push %%ebx; "
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"movl %4,%%eax; " CPUID
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"movl %%eax,%0; movl %%ebx,%1; movl %%ecx,%2; movl %%edx,%3; "
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"pop %%ebx"
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: "=m" (regs.eax), "=m" (regs.ebx), "=m" (regs.ecx), "=m" (regs.edx)
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: "g" (func)
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: "%eax", "%ecx", "%edx");
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asm( CPUID
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: "=a" (regs.eax), "=b" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx)
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: "0" (func));
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return regs;
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}
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@ -58,10 +55,29 @@ rdtsc(void)
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{
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unsigned int i, j;
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#define RDTSC ".byte 0x0f, 0x31; "
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asm(RDTSC : "=a"(i), "=d"(j) : );
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asm volatile (RDTSC : "=a"(i), "=d"(j) : );
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return ((int64_t)j<<32) + (int64_t)i;
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}
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static const char*
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brandname(int i)
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{
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const static char* brandmap[] = {
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NULL,
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"Intel(R) Celeron(R) processor",
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"Intel(R) Pentium(R) III processor",
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"Intel(R) Pentium(R) III Xeon(tm) processor",
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"Intel(R) Pentium(R) III processor",
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NULL,
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"Mobile Intel(R) Pentium(R) III processor-M",
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"Mobile Intel(R) Celeron(R) processor"
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};
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if (i >= sizeof(brandmap))
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return NULL;
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else
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return brandmap[i];
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}
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static void
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store32(char *d, unsigned int v)
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@ -82,7 +98,7 @@ main(int argc, char **argv)
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unsigned max_ext_cpuid;
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unsigned int amd_flags;
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unsigned int amd_flags2;
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char *model_name = "Unknown CPU";
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const char *model_name = NULL;
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int i;
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char processor_name[49];
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@ -96,11 +112,6 @@ main(int argc, char **argv)
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idstr[12] = 0;
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printf("vendor_id\t: %s\n", idstr);
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if (strcmp(idstr, "GenuineIntel") == 0)
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model_name = "Unknown Intel CPU";
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else if (strcmp(idstr, "AuthenticAMD") == 0)
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model_name = "Unknown AMD CPU";
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regs_ext = cpuid((1<<31) + 0);
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max_ext_cpuid = regs_ext.eax;
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if (max_ext_cpuid >= (1<<31) + 1) {
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@ -139,7 +150,7 @@ main(int argc, char **argv)
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{ 6, "pae", "Physical Address Extension" },
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{ 7, "mce", "Machine Check Exception" },
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{ 8, "cx8", "CMPXCHG8B Instruction Supported" },
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{ 9, "apic", "On-chip CPIC Hardware Enabled" },
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{ 9, "apic", "On-chip APIC Hardware Enabled" },
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{ 11, "sep", "SYSENTER and SYSEXIT" },
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{ 12, "mtrr", "Memory Type Range Registers" },
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{ 13, "pge", "PTE Global Bit" },
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@ -147,16 +158,16 @@ main(int argc, char **argv)
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{ 15, "cmov", "Conditional Move/Compare Instruction" },
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{ 16, "pat", "Page Attribute Table" },
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{ 17, "pse36", "Page Size Extension 36-bit" },
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{ 18, "psn", "Processor Serial Number" },
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{ 18, "pn", "Processor Serial Number" },
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{ 19, "cflsh", "CFLUSH instruction" },
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{ 21, "ds", "Debug Store" },
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{ 21, "dts", "Debug Store" },
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{ 22, "acpi", "Thermal Monitor and Clock Ctrl" },
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{ 23, "mmx", "MMX Technology" },
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{ 24, "fxsr", "FXSAVE/FXRSTOR" },
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{ 25, "sse", "SSE Extensions" },
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{ 26, "sse2", "SSE2 Extensions" },
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{ 27, "ss", "Self Snoop" },
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{ 28, "htt", "Multi-threading" },
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{ 28, "ht", "Multi-threading" },
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{ 29, "tm", "Therm. Monitor" },
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{ 30, "ia64", "IA-64 Processor" },
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{ 31, "pbe", "Pend. Brk. EN." },
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@ -167,14 +178,15 @@ main(int argc, char **argv)
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char *desc;
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char *description;
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} cap2[] = {
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{ 0, "sse3", "SSE3 Extensions" },
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{ 0, "pni", "SSE3 Extensions" },
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{ 3, "monitor", "MONITOR/MWAIT" },
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{ 4, "ds-cpl", "CPL Qualified Debug Store" },
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{ 4, "ds_cpl", "CPL Qualified Debug Store" },
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{ 5, "vmx", "Virtual Machine Extensions" },
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{ 7, "est", "Enhanced Intel SpeedStep Technology" },
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{ 8, "tm2", "Thermal Monitor 2" },
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{ 10, "cnxt-id", "L1 Context ID" },
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{ 13, "cmpxchg16b", "CMPXCHG16B Available" },
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{ 10, "cid", "L1 Context ID" },
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{ 13, "cx16", "CMPXCHG16B Available" },
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{ 14, "xtpr", "xTPR Disable" },
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{ -1 }
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};
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static struct {
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@ -188,8 +200,9 @@ main(int argc, char **argv)
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{ 22, "mmxext","MMX Technology (AMD Extensions)" },
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{ 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" },
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{ 27, "rdtscp", "RDTSCP Instruction" },
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{ 30, "3dnowext","3Dnow! Extensions" },
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{ 31, "3dnow", "3Dnow!" },
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{ 29, "lm", "Long Mode Capable" },
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{ 30, "3dnowext","3DNow! Extensions" },
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{ 31, "3dnow", "3DNow!" },
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{ -1 }
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};
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static struct {
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@ -200,19 +213,36 @@ main(int argc, char **argv)
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{ 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" },
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{ 1, "cmp_legacy", "Chip Multi-Core" },
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{ 2, "svm", "Secure Virtual Machine" },
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{ 4, "cr8", "CR8 Available in Legacy Mode" },
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{ 4, "cr8legacy", "CR8 Available in Legacy Mode" },
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{ -1 }
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};
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unsigned int family, model, stepping;
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regs = cpuid(1);
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family = (regs.eax >> 8) & 0xf;
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model = (regs.eax >> 4) & 0xf;
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stepping = regs.eax & 0xf;
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if (family == 0xf)
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{
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family += (regs.eax >> 20) & 0xff;
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model += ((regs.eax >> 16) & 0xf) << 4;
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}
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printf("cpu family\t: %d\n"
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"model\t\t: %d\n"
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"stepping\t: %d\n" ,
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family = (regs.eax >> 8) & 0xf,
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model = (regs.eax >> 4) & 0xf,
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stepping = regs.eax & 0xf);
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family,
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model,
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stepping);
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if (strstr(idstr, "Intel") && !model_name) {
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if (family == 6 && model == 0xb && stepping == 1)
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model_name = "Intel (R) Celeron (R) processor";
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else
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model_name = brandname(regs.ebx & 0xf);
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}
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printf("flags\t\t:");
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for (i = 0; cap[i].bit >= 0; i++) {
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if (regs.edx & (1 << cap[i].bit)) {
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@ -220,7 +250,7 @@ main(int argc, char **argv)
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}
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}
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for (i = 0; cap2[i].bit >= 0; i++) {
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if (regs.ecx & (1 << cap[i].bit)) {
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if (regs.ecx & (1 << cap2[i].bit)) {
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printf(" %s", cap2[i].desc);
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}
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}
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@ -231,7 +261,11 @@ main(int argc, char **argv)
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family == 5 &&
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(model >= 9 || model == 8 && stepping >= 8))
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printf(" %s", "k6_mtrr");
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/* similar for cyrix_arr. */
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if (strstr(idstr, "Cyrix") &&
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(family == 5 && model < 4 || family == 6))
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printf(" %s", "cyrix_arr");
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for (i = 0; cap_amd[i].bit >= 0; i++) {
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if (amd_flags & (1 << cap_amd[i].bit)) {
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printf(" %s", cap_amd[i].desc);
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@ -267,7 +301,9 @@ main(int argc, char **argv)
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}
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}
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printf("model name\t: %s\n", model_name);
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exit(0);
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printf("model name\t: ");
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if (model_name)
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printf("%s\n", model_name);
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else
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printf("Unknown %s CPU\n", idstr);
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}
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