mirror of https://github.com/mpv-player/mpv
correct k6_mtrr detection, add a great deal of infos about newer processors
patch by Zuxy Meng < zuxy POIS meng @gmail POIS com > Original thread: Date: Nov 21, 2005 11:36 AM Subject: [MPlayer-dev-eng] [PATCH] TOOLS/cpuinfo.c: correct k6_mtrr detection git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@17041 b3059339-0415-0410-9bf9-f77b7e298cf2
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@ -4,6 +4,8 @@
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#include <stdio.h>
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#include <sys/time.h>
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#include <stdlib.h>
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#include <string.h>
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#ifdef __MINGW32__
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#include <sys/timeb.h>
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@ -79,6 +81,7 @@ main(int argc, char **argv)
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unsigned max_cpuid;
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unsigned max_ext_cpuid;
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unsigned int amd_flags;
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unsigned int amd_flags2;
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char *model_name = "Unknown CPU";
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int i;
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char processor_name[49];
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@ -103,6 +106,7 @@ main(int argc, char **argv)
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if (max_ext_cpuid >= (1<<31) + 1) {
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regs_ext = cpuid((1<<31) + 1);
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amd_flags = regs_ext.edx;
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amd_flags2 = regs_ext.ecx;
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if (max_ext_cpuid >= (1<<31) + 4) {
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for (i = 2; i <= 4; i++) {
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@ -117,6 +121,7 @@ main(int argc, char **argv)
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}
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} else {
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amd_flags = 0;
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amd_flags2 = 0;
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}
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if (max_cpuid >= 1) {
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@ -151,7 +156,25 @@ main(int argc, char **argv)
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{ 25, "sse", "SSE Extensions" },
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{ 26, "sse2", "SSE2 Extensions" },
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{ 27, "ss", "Self Snoop" },
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{ 28, "htt", "Multi-threading" },
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{ 29, "tm", "Therm. Monitor" },
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{ 30, "ia64", "IA-64 Processor" },
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{ 31, "pbe", "Pend. Brk. EN." },
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;
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char *description;
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} cap2[] = {
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{ 0, "sse3", "SSE3 Extensions" },
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{ 3, "monitor", "MONITOR/MWAIT" },
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{ 4, "ds-cpl", "CPL Qualified Debug Store" },
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{ 5, "vmx", "Virtual Machine Extensions" },
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{ 7, "est", "Enhanced Intel SpeedStep Technology" },
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{ 8, "tm2", "Thermal Monitor 2" },
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{ 10, "cnxt-id", "L1 Context ID" },
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{ 13, "cmpxchg16b", "CMPXCHG16B Available" },
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{ -1 }
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};
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static struct {
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@ -159,21 +182,36 @@ main(int argc, char **argv)
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char *desc;;
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char *description;
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} cap_amd[] = {
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{ 22, "mmxext","MMX Technology (AMD Extensions)" },
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{ 11, "syscall", "SYSCALL and SYSRET" },
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{ 19, "mp", "MP Capable" },
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{ 20, "nx", "No-Execute Page Protection" },
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{ 22, "mmxext","MMX Technology (AMD Extensions)" },
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{ 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" },
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{ 27, "rdtscp", "RDTSCP Instruction" },
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{ 30, "3dnowext","3Dnow! Extensions" },
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{ 31, "3dnow", "3Dnow!" },
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{ 32, "k6_mtrr", "Memory Type Range Registers" },
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{ -1 }
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};
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int i;
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static struct {
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int bit;
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char *desc;
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char *description;
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} cap_amd2[] = {
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{ 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" },
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{ 1, "cmp_legacy", "Chip Multi-Core" },
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{ 2, "svm", "Secure Virtual Machine" },
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{ 4, "cr8", "CR8 Available in Legacy Mode" },
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{ -1 }
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};
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unsigned int family, model, stepping;
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regs = cpuid(1);
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printf("cpu family\t: %d\n"
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"model\t\t: %d\n"
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"stepping\t: %d\n" ,
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(regs.eax >> 8) & 0xf,
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(regs.eax >> 4) & 0xf,
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regs.eax & 0xf);
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family = (regs.eax >> 8) & 0xf,
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model = (regs.eax >> 4) & 0xf,
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stepping = regs.eax & 0xf);
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printf("flags\t\t:");
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for (i = 0; cap[i].bit >= 0; i++) {
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@ -181,11 +219,29 @@ main(int argc, char **argv)
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printf(" %s", cap[i].desc);
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}
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}
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for (i = 0; cap2[i].bit >= 0; i++) {
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if (regs.ecx & (1 << cap[i].bit)) {
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printf(" %s", cap2[i].desc);
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}
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}
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/* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but
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it is not indicated by a CPUID feature bit, so we
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have to check the family, model and stepping instead. */
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if (strstr(idstr, "AMD") &&
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family == 5 &&
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(model >= 9 || model == 8 && stepping >= 8))
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printf(" %s", "k6_mtrr");
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for (i = 0; cap_amd[i].bit >= 0; i++) {
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if (amd_flags & (1 << cap_amd[i].bit)) {
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printf(" %s", cap_amd[i].desc);
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}
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}
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for (i = 0; cap_amd2[i].bit >= 0; i++) {
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if (amd_flags2 & (1 << cap_amd2[i].bit)) {
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printf(" %s", cap_amd2[i].desc);
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}
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}
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printf("\n");
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if (regs.edx & (1 << 4)) {
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