mirror of https://github.com/mpv-player/mpv
Merge with Ani Joshi's radeonfb-0.1.0
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@1915 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
cbe0cf8827
commit
6883c2ead8
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@ -488,6 +488,12 @@
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#define MEM_REQ_LOCK 0x00800000
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/* SURFACE_CNTL bit constants */
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#define SURF_TRANSLATION_DIS (1 << 8)
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#define NONSURF_AP0_SWP_16BPP (1 << 20)
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#define NONSURF_AP0_SWP_32BPP (2 << 20)
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/* RBBM_SOFT_RESET bit constants */
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#define SOFT_RESET_CP (1 << 0)
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#define SOFT_RESET_HI (1 << 1)
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@ -630,7 +636,9 @@
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#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
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#define GMC_SRC_DATATYPE_COLOR (3 << 12)
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#define ROP3_S 0x00cc0000
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#define ROP3_SRCCOPY 0x00cc0000
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#define ROP3_P 0x00f00000
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#define ROP3_PATCOPY 0x00f00000
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#define DP_SRC_SOURCE_MASK (7 << 24)
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#define GMC_BRUSH_NONE (15 << 4)
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#define DP_SRC_SOURCE_MEMORY (2 << 24)
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@ -641,7 +649,6 @@
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#define DP_SRC_HOST 0x00000300
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#define DP_SRC_HOST_BYTEALIGN 0x00000400
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#define ROP3_PATCOPY 0x00f00000
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/* masks */
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@ -11,6 +11,8 @@
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* 2001-02-19 mode bug fixes, 0.0.7
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* 2001-07-05 fixed scrolling issues, engine initialization,
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* and minor mode tweaking, 0.0.9
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* 2001-09-06 console switching fixes, blanking fixes,
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* 0.1.0
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*
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* 2001-09-07 Radeon VE support
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* 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
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@ -21,14 +23,16 @@
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* of other bugs. Probably they can be solved by
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* importing XFree86 code, which has ATI's support).,
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* 0.0.11
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*
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* 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
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* console switching fixes, blanking fixes,
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* 0.1.0-ve.0
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*
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* Special thanks to ATI DevRel team for their hardware donations.
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*
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*/
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#define RADEON_VERSION "0.0.11"
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#define RADEON_VERSION "0.1.0-ve.0"
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#include <linux/config.h>
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@ -173,6 +177,7 @@ struct radeon_regs {
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int bpp;
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u32 crtc_gen_cntl;
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u32 crtc_ext_cntl;
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u32 surface_cntl;
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u32 dac_cntl;
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u32 dda_config;
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u32 dda_on_off;
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@ -217,11 +222,17 @@ struct radeonfb_info {
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struct ram_info ram;
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u32 hack_crtc_ext_cntl;
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u32 hack_crtc_v_sync_strt_wid;
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#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
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union {
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#if defined(FBCON_HAS_CFB16)
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u_int16_t cfb16[16];
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#endif
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#if defined(FBCON_HAS_CFB24)
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u_int32_t cfb24[16];
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#endif
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#if defined(FBCON_HAS_CFB32)
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u_int32_t cfb32[16];
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#endif
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@ -338,6 +349,8 @@ static __inline__ u32 radeon_get_dstbpp(u16 depth)
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return DST_15BPP;
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case 16:
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return DST_16BPP;
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case 24:
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return DST_24BPP;
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case 32:
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return DST_32BPP;
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default:
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@ -460,10 +473,11 @@ static char fontname[40] __initdata;
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static char *mode_option __initdata;
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static char noaccel __initdata = 0;
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#if 0
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#ifdef FBCON_HAS_CFB8
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static struct display_switch fbcon_radeon8;
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#endif
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#endif
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/*
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* prototypes
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@ -492,7 +506,7 @@ static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
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struct fb_info *info);
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static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
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unsigned blue, unsigned transp, struct fb_info *info);
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static void radeon_set_dispsw (struct radeonfb_info *rinfo);
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static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
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static void radeon_save_state (struct radeonfb_info *rinfo,
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struct radeon_regs *save);
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static void radeon_engine_init (struct radeonfb_info *rinfo);
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@ -508,7 +522,11 @@ static int radeonfb_pci_register (struct pci_dev *pdev,
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static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
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static char *radeon_find_rom(struct radeonfb_info *rinfo);
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static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
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static void do_install_cmap(int con, struct fb_info *info);
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static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
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struct fb_var_screeninfo *var,
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struct fb_var_screeninfo *v,
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int nom, int den);
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static struct fb_ops radeon_fb_ops = {
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fb_get_fix: radeonfb_get_fix,
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@ -810,6 +828,7 @@ static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
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static char *radeon_find_rom(struct radeonfb_info *rinfo)
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{
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#if defined(__i386__)
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u32 segstart;
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char *rom_base;
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char *rom;
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@ -818,7 +837,6 @@ static char *radeon_find_rom(struct radeonfb_info *rinfo)
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char aty_rom_sig[] = "761295520";
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char radeon_sig[] = "RG6";
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#if defined(__i386__)
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for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
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stage = 1;
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@ -998,7 +1016,7 @@ static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
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disp->var = radeonfb_default_var;
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info->disp = disp;
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radeon_set_dispsw (rinfo);
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radeon_set_dispsw (rinfo, disp);
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if (noaccel)
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disp->scrollmode = SCROLL_YREDRAW;
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@ -1035,10 +1053,8 @@ static int radeon_init_disp_var (struct radeonfb_info *rinfo)
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}
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static void radeon_set_dispsw (struct radeonfb_info *rinfo)
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static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
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{
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struct display *disp = &rinfo->disp;
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int accel;
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accel = disp->var.accel_flags & FB_ACCELF_TEXT;
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@ -1057,7 +1073,7 @@ static void radeon_set_dispsw (struct radeonfb_info *rinfo)
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switch (disp->var.bits_per_pixel) {
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#ifdef FBCON_HAS_CFB8
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case 8:
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disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
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disp->dispsw = &fbcon_cfb8;
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disp->visual = FB_VISUAL_PSEUDOCOLOR;
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disp->line_length = disp->var.xres_virtual;
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break;
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@ -1070,6 +1086,14 @@ static void radeon_set_dispsw (struct radeonfb_info *rinfo)
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disp->line_length = disp->var.xres_virtual * 2;
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break;
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#endif
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#ifdef FBCON_HAS_CFB32
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case 24:
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disp->dispsw = &fbcon_cfb24;
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disp->dispsw_data = &rinfo->con_cmap.cfb24;
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disp->visual = FB_VISUAL_DIRECTCOLOR;
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disp->line_length = disp->var.xres_virtual * 4;
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break;
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#endif
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#ifdef FBCON_HAS_CFB32
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case 32:
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disp->dispsw = &fbcon_cfb32;
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@ -1146,19 +1170,8 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
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struct display *disp;
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struct fb_var_screeninfo v;
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int nom, den, i, accel;
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int nom, den, accel;
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unsigned chgvar = 0;
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static struct {
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int xres, yres;
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} modes[] = {
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{
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1600, 1280}, {
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1280, 1024}, {
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1024, 768}, {
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800, 600}, {
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640, 480}, {
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-1, -1}
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};
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disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
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@ -1169,6 +1182,7 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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(disp->var.yres != var->yres) ||
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(disp->var.xres_virtual != var->xres_virtual) ||
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(disp->var.yres_virtual != var->yres_virtual) ||
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(disp->var.bits_per_pixel != var->bits_per_pixel) ||
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memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
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memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
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memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
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@ -1179,21 +1193,17 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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switch (v.bits_per_pixel) {
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#ifdef FBCON_HAS_CFB8
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case 8:
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v.bits_per_pixel = 8;
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disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
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nom = den = 1;
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disp->line_length = v.xres_virtual;
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disp->visual = FB_VISUAL_PSEUDOCOLOR;
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v.red.offset = v.green.offset = v.blue.offset = 0;
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v.red.length = v.green.length = v.blue.length = 8;
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v.transp.offset = v.transp.length = 0;
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break;
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#endif
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#ifdef FBCON_HAS_CFB16
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case 16:
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v.bits_per_pixel = 16;
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disp->dispsw = &fbcon_cfb16;
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disp->dispsw_data = &rinfo->con_cmap.cfb16;
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nom = 2;
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den = 1;
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disp->line_length = v.xres_virtual * 2;
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@ -1204,14 +1214,25 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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v.red.length = 5;
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v.green.length = 6;
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v.blue.length = 5;
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v.transp.offset = v.transp.length = 0;
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break;
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#endif
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#ifdef FBCON_HAS_CFB24
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case 24:
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nom = 4;
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den = 1;
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disp->line_length = v.xres_virtual * 3;
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disp->visual = FB_VISUAL_DIRECTCOLOR;
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v.red.offset = 16;
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v.green.offset = 8;
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v.blue.offset = 0;
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v.red.length = v.blue.length = v.green.length = 8;
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v.transp.offset = v.transp.length = 0;
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break;
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#endif
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#ifdef FBCON_HAS_CFB32
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case 32:
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v.bits_per_pixel = 32;
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disp->dispsw = &fbcon_cfb32;
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disp->dispsw_data = rinfo->con_cmap.cfb32;
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nom = 4;
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den = 1;
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disp->line_length = v.xres_virtual * 4;
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@ -1220,6 +1241,8 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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v.green.offset = 8;
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v.blue.offset = 0;
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v.red.length = v.blue.length = v.green.length = 8;
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v.transp.offset = 24;
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v.transp.length = 8;
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break;
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#endif
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default:
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@ -1228,28 +1251,8 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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return -EINVAL;
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}
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if (v.xres * nom / den * v.yres > (rinfo->video_ram)) {
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printk ("radeonfb: mode %dx%dx%d rejected, not enough video ram\n",
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var->xres, var->yres, var->bits_per_pixel);
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return -EINVAL;
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}
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if (v.xres_virtual == -1 && v.yres_virtual == -1) {
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printk ("radeonfb: using maximum available virtual resolution\n");
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for (i = 0; modes[i].xres != -1; i++) {
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if (modes[i].xres * nom / den * modes[i].yres < (rinfo->video_ram/2))
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break;
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}
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if (modes[i].xres == -1) {
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printk ("radeonfb: could not find a virtual res\n");
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return -EINVAL;
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}
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v.xres_virtual = modes[i].xres;
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v.yres_virtual = modes[i].yres;
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printk ("radeonfb: virtual resolution set to maximum of %dx%d\n",
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v.xres_virtual, v.yres_virtual);
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}
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if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
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return -EINVAL;
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if (v.xoffset < 0)
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v.xoffset = 0;
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@ -1276,15 +1279,24 @@ static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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return -EINVAL;
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}
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disp->type = FB_TYPE_PACKED_PIXELS;
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memcpy (&disp->var, &v, sizeof (v));
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if (chgvar) {
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radeon_set_dispsw(rinfo, disp);
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if (noaccel)
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disp->scrollmode = SCROLL_YREDRAW;
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else
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disp->scrollmode = 0;
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if (info && info->changevar)
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info->changevar(con);
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}
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radeon_load_video_mode (rinfo, &v);
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if (chgvar && info && info->changevar)
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info->changevar (con);
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do_install_cmap(con, info);
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return 0;
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}
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|
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@ -1343,41 +1355,100 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
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struct fb_info *info)
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{
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struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
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struct display *disp;
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unsigned int base;
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disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
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if (var->xoffset > (var->xres_virtual - var->xres))
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return -EINVAL;
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if (var->yoffset > (var->yres_virtual - var->yres))
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return -EINVAL;
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|
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if (var->vmode & FB_VMODE_YWRAP) {
|
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if (var->yoffset < 0 ||
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var->yoffset >= disp->var.yres_virtual ||
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var->xoffset )
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return -EINVAL;
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} else {
|
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if (var->xoffset + disp->var.xres > disp->var.xres_virtual ||
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var->yoffset + disp->var.yres > disp->var.yres_virtual)
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return -EINVAL;
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}
|
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u32 offset, xoffset, yoffset;
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base = var->yoffset * disp->line_length + var->xoffset;
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disp->var.xoffset = var->xoffset;
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disp->var.yoffset = var->yoffset;
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xoffset = (var->xoffset + 7) & ~7;
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yoffset = var->yoffset;
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|
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if (var->vmode & FB_VMODE_YWRAP)
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disp->var.vmode |= FB_VMODE_YWRAP;
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else
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disp->var.vmode &= ~FB_VMODE_YWRAP;
|
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if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
|
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var->yres_virtual))
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return -EINVAL;
|
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|
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offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
|
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OUTREG(CRTC_OFFSET, offset);
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return 0;
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}
|
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|
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|
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static void do_install_cmap(int con, struct fb_info *info)
|
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{
|
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struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
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|
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if (con != rinfo->currcon)
|
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return;
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|
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if (fb_display[con].cmap.len)
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fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
|
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else {
|
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int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
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fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
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}
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}
|
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|
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|
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static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
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struct fb_var_screeninfo *var,
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struct fb_var_screeninfo *v,
|
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int nom, int den)
|
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{
|
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static struct {
|
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int xres, yres;
|
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} modes[] = {
|
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{1600, 1280},
|
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{1280, 1024},
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{1024, 768},
|
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{800, 600},
|
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{640, 480},
|
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{-1, -1}
|
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};
|
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int i;
|
||||
|
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/* use highest possible virtual resolution */
|
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if (v->xres_virtual == -1 && v->yres_virtual == -1) {
|
||||
printk("radeonfb: using max availabe virtual resolution\n");
|
||||
for (i=0; modes[i].xres != -1; i++) {
|
||||
if (modes[i].xres * nom / den * modes[i].yres <
|
||||
rinfo->video_ram / 2)
|
||||
break;
|
||||
}
|
||||
if (modes[i].xres == -1) {
|
||||
printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
v->xres_virtual = modes[i].xres;
|
||||
v->yres_virtual = modes[i].yres;
|
||||
|
||||
printk("radeonfb: virtual resolution set to max of %dx%d\n",
|
||||
v->xres_virtual, v->yres_virtual);
|
||||
} else if (v->xres_virtual == -1) {
|
||||
v->xres_virtual = (rinfo->video_ram * den /
|
||||
(nom * v->yres_virtual * 2)) & ~15;
|
||||
} else if (v->yres_virtual == -1) {
|
||||
v->xres_virtual = (v->xres_virtual + 15) & ~15;
|
||||
v->yres_virtual = rinfo->video_ram * den /
|
||||
(nom * v->xres_virtual *2);
|
||||
} else {
|
||||
if (v->xres_virtual * nom / den * v->yres_virtual >
|
||||
rinfo->video_ram) {
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
if (v->xres_virtual * nom / den >= 8192) {
|
||||
v->xres_virtual = 8192 * den / nom - 16;
|
||||
}
|
||||
|
||||
if (v->xres_virtual < v->xres)
|
||||
return -EINVAL;
|
||||
|
||||
if (v->yres_virtual < v->yres)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
||||
unsigned long arg, int con, struct fb_info *info)
|
||||
|
|
@ -1393,7 +1464,7 @@ static int radeonfb_switch (int con, struct fb_info *info)
|
|||
struct display *disp;
|
||||
struct fb_cmap *cmap;
|
||||
int switchcon = 0;
|
||||
|
||||
|
||||
disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
||||
|
||||
if (rinfo->currcon >= 0) {
|
||||
|
|
@ -1414,9 +1485,16 @@ static int radeonfb_switch (int con, struct fb_info *info)
|
|||
disp->var.activate = FB_ACTIVATE_NOW;
|
||||
|
||||
radeonfb_set_var (&disp->var, con, info);
|
||||
radeon_set_dispsw (rinfo);
|
||||
radeon_set_dispsw (rinfo, disp);
|
||||
do_install_cmap(con, info);
|
||||
}
|
||||
|
||||
|
||||
/* XXX absurd hack for X to restore console */
|
||||
{
|
||||
OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
||||
OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1435,25 +1513,28 @@ static int radeonfb_updatevar (int con, struct fb_info *info)
|
|||
static void radeonfb_blank (int blank, struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
||||
u8 mode = 0;
|
||||
u32 val = INREG(CRTC_EXT_CNTL);
|
||||
|
||||
/* reset it */
|
||||
val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
|
||||
CRTC_VSYNC_DIS);
|
||||
|
||||
switch (blank) {
|
||||
case 0:
|
||||
/* unblank */
|
||||
mode = 0;
|
||||
case VESA_NO_BLANKING:
|
||||
break;
|
||||
case 1:
|
||||
/* blank */
|
||||
mode = ((INREG8(CRTC_EXT_CNTL + 1) & 3) | 4);
|
||||
case VESA_VSYNC_SUSPEND:
|
||||
val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
mode = blank | 4;
|
||||
case VESA_HSYNC_SUSPEND:
|
||||
val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
|
||||
break;
|
||||
case VESA_POWERDOWN:
|
||||
val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
|
||||
CRTC_HSYNC_DIS);
|
||||
break;
|
||||
}
|
||||
|
||||
OUTREG8(CRTC_EXT_CNTL + 1, mode);
|
||||
OUTREG(CRTC_EXT_CNTL, val);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1502,7 +1583,7 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|||
unsigned blue, unsigned transp, struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
||||
u32 pindex, col;
|
||||
u32 pindex;
|
||||
|
||||
if (regno > 255)
|
||||
return 1;
|
||||
|
|
@ -1517,18 +1598,33 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|||
/* init gamma for hicolor */
|
||||
if ((rinfo->depth > 8) && (regno == 0)) {
|
||||
int i;
|
||||
u32 tmp;
|
||||
|
||||
for (i=0; i<255; i++) {
|
||||
OUTREG(PALETTE_INDEX, i);
|
||||
tmp = (i << 16) | (i << 8) | i;
|
||||
radeon_fifo_wait(32);
|
||||
OUTREG(PALETTE_DATA, tmp);
|
||||
OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
|
||||
}
|
||||
}
|
||||
|
||||
/* default */
|
||||
pindex = regno;
|
||||
|
||||
/* XXX actually bpp, fixme */
|
||||
if (rinfo->depth == 16)
|
||||
pindex = regno * 8;
|
||||
|
||||
if (rinfo->depth == 16) {
|
||||
OUTREG(PALETTE_INDEX, pindex/2);
|
||||
OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
|
||||
(green << 8) | (rinfo->palette[regno/2].blue));
|
||||
green = rinfo->palette[regno/2].green;
|
||||
}
|
||||
|
||||
if ((rinfo->depth == 8) || (regno < 32)) {
|
||||
OUTREG(PALETTE_INDEX, pindex);
|
||||
OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
|
||||
}
|
||||
|
||||
#if 0
|
||||
col = (red << 16) | (green << 8) | blue;
|
||||
|
||||
if (rinfo->depth == 16) {
|
||||
|
|
@ -1548,16 +1644,22 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|||
OUTREG8(PALETTE_INDEX, pindex);
|
||||
radeon_fifo_wait(32);
|
||||
OUTREG(PALETTE_DATA, col);
|
||||
#endif
|
||||
|
||||
#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
||||
if (regno < 32) {
|
||||
switch (rinfo->depth) {
|
||||
#ifdef FBCON_HAS_CFB16
|
||||
case 16:
|
||||
rinfo->con_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
|
||||
rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
|
||||
regno;
|
||||
break;
|
||||
#endif
|
||||
#ifdef FBCON_HAS_CFB24
|
||||
case 24:
|
||||
rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
|
||||
break;
|
||||
#endif
|
||||
#ifdef FBCON_HAS_CFB32
|
||||
case 32: {
|
||||
u32 i;
|
||||
|
|
@ -1632,21 +1734,14 @@ static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|||
hsync_wid = 1;
|
||||
else if (hsync_wid > 0x3f) /* max */
|
||||
hsync_wid = 0x3f;
|
||||
|
||||
vsync_wid = mode->vsync_len;
|
||||
if (vsync_wid == 0)
|
||||
vsync_wid = 1;
|
||||
else if (vsync_wid > 0x1f) /* max */
|
||||
vsync_wid = 0x1f;
|
||||
|
||||
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
||||
hSyncPol = 1;
|
||||
else
|
||||
hSyncPol = 0;
|
||||
|
||||
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
||||
vSyncPol = 1;
|
||||
else
|
||||
vSyncPol = 0;
|
||||
hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
||||
vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
||||
|
||||
cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
||||
|
||||
|
|
@ -1684,16 +1779,29 @@ static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|||
(((mode->xres / 8) - 1) << 16));
|
||||
|
||||
newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
|
||||
(hsync_wid << 16) | (hSyncPol << 23));
|
||||
(hsync_wid << 16) | (h_sync_pol << 23));
|
||||
|
||||
newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
||||
((mode->yres - 1) << 16);
|
||||
|
||||
newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
|
||||
(vsync_wid << 16) | (vSyncPol << 23));
|
||||
(vsync_wid << 16) | (v_sync_pol << 23));
|
||||
|
||||
newmode.crtc_pitch = (mode->xres >> 3);
|
||||
|
||||
newmode.surface_cntl = SURF_TRANSLATION_DIS;
|
||||
#if defined(__BIG_ENDIAN)
|
||||
switch (mode->bits_per_pixel) {
|
||||
case 16:
|
||||
newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
||||
& ~(0x3f)) / 64;
|
||||
|
||||
|
|
@ -1706,6 +1814,8 @@ static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|||
newmode.yres = mode->yres;
|
||||
|
||||
rinfo->bpp = mode->bits_per_pixel;
|
||||
rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
|
||||
rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
|
||||
|
||||
if (freq > rinfo->pll.ppll_max)
|
||||
freq = rinfo->pll.ppll_max;
|
||||
|
|
@ -1808,6 +1918,7 @@ static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|||
OUTREG(CRTC_OFFSET, 0);
|
||||
OUTREG(CRTC_OFFSET_CNTL, 0);
|
||||
OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
||||
OUTREG(SURFACE_CNTL, mode->surface_cntl);
|
||||
|
||||
while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
|
||||
PPLL_DIV_SEL_MASK) {
|
||||
|
|
@ -1844,7 +1955,7 @@ static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|||
return;
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
|
||||
/*
|
||||
* text console acceleration
|
||||
|
|
@ -1896,7 +2007,6 @@ static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|||
{
|
||||
struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
||||
u32 clr;
|
||||
u32 temp;
|
||||
|
||||
clr = attr_bgcol_ec(p, conp);
|
||||
clr |= (clr << 8);
|
||||
|
|
@ -1934,3 +2044,5 @@ static struct display_switch fbcon_radeon8 = {
|
|||
fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* 0 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue