ffmpeg/tests
Rémi Denis-Courmont 0c0a3deb18 lavu/cpu: CPU flags for the RISC-V Vector extension
RVV defines a total of 12 different extensions, including:

- 5 different instruction subsets:
  - Zve32x: 8-, 16- and 32-bit integers,
  - Zve32f: Zve32x plus single precision floats,
  - Zve64x: Zve32x plus 64-bit integers,
  - Zve64f: Zve32f plus Zve64x,
  - Zve64d: Zve64f plus double precision floats.

- 6 different vector lengths:
  - Zvl32b (embedded only),
  - Zvl64b (embedded only),
  - Zvl128b,
  - Zvl256b,
  - Zvl512b,
  - Zvl1024b,

- and the V extension proper: equivalent to Zve64f and Zvl128b.

In total, there are 6 different possible sets of supported instructions
(including the empty set), but for convenience we allocate one bit for
each type sets: up-to-32-bit ints (RVV_I32), floats (RVV_F32),
64-bit ints (RVV_I64) and doubles (RVV_F64).

Whence the vector size is needed, it can be retrieved by reading the
unprivileged read-only vlenb CSR. This should probably be a separate
helper macro if needed at a later point.
2022-09-27 13:19:52 +02:00
..
api
checkasm lavu/cpu: CPU flags for the RISC-V Vector extension 2022-09-27 13:19:52 +02:00
fate fate/cbs: Add tests for h264_redundant_pps BSF 2022-09-25 14:56:08 +02:00
filtergraphs
ref avutil: add RGBA single-float precision packed formats 2022-09-25 18:34:48 +02:00
.gitignore
Makefile fate/segafilm: Add tests for segafilm (de)muxer 2022-09-20 18:32:28 +02:00
audiogen.c
audiomatch.c
base64.c
copycooker.sh
extended.ffconcat
fate-run.sh tests/fate-run: Allow to set input options for encoding pass 2022-09-10 01:38:07 +02:00
fate-valgrind.supp
fate.sh
md5.sh
refcmp-metadata.awk
reference.pnm
rotozoom.c
simple1.ffconcat
simple2.ffconcat
test.ffmeta
tiny_psnr.c
tiny_ssim.c
utils.c
videogen.c