mirror of https://git.ffmpeg.org/ffmpeg.git
1427 lines
70 KiB
C
1427 lines
70 KiB
C
/*
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* Copyright (c) 2015 Manojkumar Bhosale (Manojkumar.Bhosale@imgtec.com)
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVUTIL_MIPS_GENERIC_MACROS_MSA_H
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#define AVUTIL_MIPS_GENERIC_MACROS_MSA_H
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#include <stdint.h>
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#include <msa.h>
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#define LOAD_UB(psrc) \
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( { \
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v16u8 out_m; \
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out_m = *((v16u8 *) (psrc)); \
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out_m; \
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} )
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#define LOAD_SB(psrc) \
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( { \
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v16i8 out_m; \
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out_m = *((v16i8 *) (psrc)); \
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out_m; \
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} )
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#define LOAD_UH(psrc) *((const v8u16 *)(psrc))
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#define LOAD_SH(psrc) \
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( { \
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v8i16 out_m; \
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out_m = *((v8i16 *) (psrc)); \
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out_m; \
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} )
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#define LOAD_SW(psrc) *((const v4i32 *)(psrc))
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#define STORE_UB(vec, pdest) *((v16u8 *)(pdest)) = (vec)
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#define STORE_SB(vec, pdest) *((v16i8 *)(pdest)) = (vec)
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#define STORE_SH(vec, pdest) \
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{ \
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*((v8i16 *) (pdest)) = (vec); \
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}
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#define STORE_SW(vec, pdest) \
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{ \
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*((v4i32 *) (pdest)) = (vec); \
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}
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#if (__mips_isa_rev >= 6)
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#define LOAD_WORD(psrc) \
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( { \
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uint8_t *src_m = (uint8_t *) (psrc); \
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uint32_t val_m; \
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\
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__asm__ volatile ( \
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"lw %[val_m], %[src_m] \n\t" \
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\
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: [val_m] "=r" (val_m) \
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: [src_m] "m" (*src_m) \
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); \
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\
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val_m; \
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} )
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#if (__mips == 64)
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#define LOAD_DWORD(psrc) \
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( { \
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uint8_t *src_m = (uint8_t *) (psrc); \
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uint64_t val_m = 0; \
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\
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__asm__ volatile ( \
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"ld %[val_m], %[src_m] \n\t" \
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\
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: [val_m] "=r" (val_m) \
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: [src_m] "m" (*src_m) \
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); \
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\
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val_m; \
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} )
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#else
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#define LOAD_DWORD(psrc) \
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( { \
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uint8_t *src1_m = (uint8_t *) (psrc); \
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uint8_t *src2_m = ((uint8_t *) (psrc)) + 4; \
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uint32_t val0_m, val1_m; \
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uint64_t genval_m = 0; \
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\
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__asm__ volatile ( \
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"lw %[val0_m], %[src1_m] \n\t" \
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\
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: [val0_m] "=r" (val0_m) \
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: [src1_m] "m" (*src1_m) \
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); \
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\
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__asm__ volatile ( \
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"lw %[val1_m], %[src2_m] \n\t" \
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\
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: [val1_m] "=r" (val1_m) \
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: [src2_m] "m" (*src2_m) \
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); \
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\
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genval_m = (uint64_t) (val1_m); \
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genval_m = (uint64_t) ((genval_m << 32) & 0xFFFFFFFF00000000); \
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genval_m = (uint64_t) (genval_m | (uint64_t) val0_m); \
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\
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genval_m; \
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} )
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#endif
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#define STORE_WORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint32_t val_m = (val); \
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\
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__asm__ volatile ( \
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"sw %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#define STORE_DWORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint64_t val_m = (val); \
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\
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__asm__ volatile ( \
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"sd %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#define STORE_HWORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint16_t val_m = (val); \
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\
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__asm__ volatile ( \
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"sh %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#else
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#define LOAD_WORD(psrc) \
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( { \
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uint8_t *src_m = (uint8_t *) (psrc); \
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uint32_t val_m; \
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\
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__asm__ volatile ( \
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"ulw %[val_m], %[src_m] \n\t" \
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\
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: [val_m] "=r" (val_m) \
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: [src_m] "m" (*src_m) \
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); \
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\
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val_m; \
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} )
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#if (__mips == 64)
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#define LOAD_DWORD(psrc) \
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( { \
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uint8_t *src_m = (uint8_t *) (psrc); \
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uint64_t val_m = 0; \
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\
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__asm__ volatile ( \
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"uld %[val_m], %[src_m] \n\t" \
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\
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: [val_m] "=r" (val_m) \
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: [src_m] "m" (*src_m) \
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); \
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\
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val_m; \
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} )
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#else
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#define LOAD_DWORD(psrc) \
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( { \
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uint8_t *src1_m = (uint8_t *) (psrc); \
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uint8_t *src2_m = ((uint8_t *) (psrc)) + 4; \
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uint32_t val0_m, val1_m; \
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uint64_t genval_m = 0; \
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\
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__asm__ volatile ( \
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"ulw %[val0_m], %[src1_m] \n\t" \
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\
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: [val0_m] "=r" (val0_m) \
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: [src1_m] "m" (*src1_m) \
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); \
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\
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__asm__ volatile ( \
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"ulw %[val1_m], %[src2_m] \n\t" \
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\
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: [val1_m] "=r" (val1_m) \
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: [src2_m] "m" (*src2_m) \
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); \
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\
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genval_m = (uint64_t) (val1_m); \
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genval_m = (uint64_t) ((genval_m << 32) & 0xFFFFFFFF00000000); \
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genval_m = (uint64_t) (genval_m | (uint64_t) val0_m); \
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\
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genval_m; \
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} )
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#endif
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#define STORE_WORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint32_t val_m = (val); \
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\
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__asm__ volatile ( \
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"usw %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#define STORE_DWORD(pdst, val) \
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{ \
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uint8_t *dst1_m = (uint8_t *) (pdst); \
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uint8_t *dst2_m = ((uint8_t *) (pdst)) + 4; \
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uint32_t val0_m, val1_m; \
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\
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val0_m = (uint32_t) ((val) & 0x00000000FFFFFFFF); \
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val1_m = (uint32_t) (((val) >> 32) & 0x00000000FFFFFFFF); \
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\
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__asm__ volatile ( \
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"usw %[val0_m], %[dst1_m] \n\t" \
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"usw %[val1_m], %[dst2_m] \n\t" \
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\
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: [dst1_m] "=m" (*dst1_m), [dst2_m] "=m" (*dst2_m) \
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: [val0_m] "r" (val0_m), [val1_m] "r" (val1_m) \
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); \
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}
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#define STORE_HWORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint16_t val_m = (val); \
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\
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__asm__ volatile ( \
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"ush %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#endif
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#define LOAD_4WORDS_WITH_STRIDE(psrc, src_stride, \
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src0, src1, src2, src3) \
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{ \
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src0 = LOAD_WORD(psrc + 0 * src_stride); \
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src1 = LOAD_WORD(psrc + 1 * src_stride); \
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src2 = LOAD_WORD(psrc + 2 * src_stride); \
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src3 = LOAD_WORD(psrc + 3 * src_stride); \
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}
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#define LOAD_2VECS_UB(psrc, stride, \
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val0, val1) \
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{ \
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val0 = LOAD_UB(psrc + 0 * stride); \
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val1 = LOAD_UB(psrc + 1 * stride); \
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}
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#define LOAD_2VECS_SB(psrc, stride, \
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val0, val1) \
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{ \
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val0 = LOAD_SB(psrc + 0 * stride); \
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val1 = LOAD_SB(psrc + 1 * stride); \
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}
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#define LOAD_3VECS_UB(psrc, stride, \
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val0, val1, val2) \
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{ \
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val0 = LOAD_UB(psrc + 0 * stride); \
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val1 = LOAD_UB(psrc + 1 * stride); \
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val2 = LOAD_UB(psrc + 2 * stride); \
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}
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#define LOAD_3VECS_SB(psrc, stride, \
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val0, val1, val2) \
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{ \
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val0 = LOAD_SB(psrc + 0 * stride); \
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val1 = LOAD_SB(psrc + 1 * stride); \
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val2 = LOAD_SB(psrc + 2 * stride); \
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}
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#define LOAD_4VECS_UB(psrc, stride, \
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val0, val1, val2, val3) \
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{ \
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val0 = LOAD_UB(psrc + 0 * stride); \
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val1 = LOAD_UB(psrc + 1 * stride); \
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val2 = LOAD_UB(psrc + 2 * stride); \
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val3 = LOAD_UB(psrc + 3 * stride); \
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}
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#define LOAD_4VECS_SB(psrc, stride, \
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val0, val1, val2, val3) \
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{ \
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val0 = LOAD_SB(psrc + 0 * stride); \
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val1 = LOAD_SB(psrc + 1 * stride); \
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val2 = LOAD_SB(psrc + 2 * stride); \
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val3 = LOAD_SB(psrc + 3 * stride); \
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}
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#define LOAD_5VECS_UB(psrc, stride, \
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out0, out1, out2, out3, out4) \
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{ \
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LOAD_4VECS_UB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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out4 = LOAD_UB(psrc + 4 * stride); \
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}
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#define LOAD_5VECS_SB(psrc, stride, \
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out0, out1, out2, out3, out4) \
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{ \
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LOAD_4VECS_SB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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out4 = LOAD_SB(psrc + 4 * stride); \
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}
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#define LOAD_6VECS_SB(psrc, stride, \
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out0, out1, out2, out3, out4, out5) \
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{ \
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LOAD_4VECS_SB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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LOAD_2VECS_SB((psrc + 4 * stride), (stride), \
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(out4), (out5)); \
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}
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#define LOAD_7VECS_UB(psrc, stride, \
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val0, val1, val2, val3, \
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val4, val5, val6) \
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{ \
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val0 = LOAD_UB((psrc) + 0 * (stride)); \
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val1 = LOAD_UB((psrc) + 1 * (stride)); \
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val2 = LOAD_UB((psrc) + 2 * (stride)); \
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val3 = LOAD_UB((psrc) + 3 * (stride)); \
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val4 = LOAD_UB((psrc) + 4 * (stride)); \
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val5 = LOAD_UB((psrc) + 5 * (stride)); \
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val6 = LOAD_UB((psrc) + 6 * (stride)); \
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}
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#define LOAD_7VECS_SB(psrc, stride, \
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val0, val1, val2, val3, \
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val4, val5, val6) \
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{ \
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val0 = LOAD_SB((psrc) + 0 * (stride)); \
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val1 = LOAD_SB((psrc) + 1 * (stride)); \
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val2 = LOAD_SB((psrc) + 2 * (stride)); \
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val3 = LOAD_SB((psrc) + 3 * (stride)); \
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val4 = LOAD_SB((psrc) + 4 * (stride)); \
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val5 = LOAD_SB((psrc) + 5 * (stride)); \
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val6 = LOAD_SB((psrc) + 6 * (stride)); \
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}
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#define LOAD_8VECS_UB(psrc, stride, \
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out0, out1, out2, out3, \
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out4, out5, out6, out7) \
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{ \
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LOAD_4VECS_UB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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LOAD_4VECS_UB((psrc + 4 * stride), (stride), \
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(out4), (out5), (out6), (out7)); \
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}
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#define LOAD_8VECS_SB(psrc, stride, \
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out0, out1, out2, out3, \
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out4, out5, out6, out7) \
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{ \
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LOAD_4VECS_SB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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LOAD_4VECS_SB((psrc + 4 * stride), (stride), \
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(out4), (out5), (out6), (out7)); \
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}
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#define LOAD_2VECS_UH(psrc, stride, \
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val0, val1) \
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{ \
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val0 = LOAD_UH((psrc) + 0 * (stride)); \
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val1 = LOAD_UH((psrc) + 1 * (stride)); \
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}
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#define LOAD_2VECS_SH(psrc, stride, \
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val0, val1) \
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{ \
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val0 = LOAD_SH((psrc) + 0 * (stride)); \
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val1 = LOAD_SH((psrc) + 1 * (stride)); \
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}
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#define LOAD_4VECS_UH(psrc, stride, \
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val0, val1, val2, val3) \
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{ \
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LOAD_2VECS_UH((psrc), (stride), val0, val1); \
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LOAD_2VECS_UH((psrc + 2 * stride), (stride), val2, val3); \
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}
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#define LOAD_4VECS_SH(psrc, stride, \
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val0, val1, val2, val3) \
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{ \
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LOAD_2VECS_SH((psrc), (stride), val0, val1); \
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LOAD_2VECS_SH((psrc + 2 * stride), (stride), val2, val3); \
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}
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#define LOAD_6VECS_SH(psrc, stride, \
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val0, val1, val2, val3, val4, val5) \
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{ \
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LOAD_2VECS_SH((psrc), (stride), val0, val1); \
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LOAD_2VECS_SH((psrc + 2 * stride), (stride), val2, val3); \
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LOAD_2VECS_SH((psrc + 4 * stride), (stride), val4, val5); \
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}
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#define LOAD_8VECS_UH(psrc, stride, \
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val0, val1, val2, val3, \
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val4, val5, val6, val7) \
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{ \
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LOAD_4VECS_UH((psrc), (stride), \
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val0, val1, val2, val3); \
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LOAD_4VECS_UH((psrc + 4 * stride), (stride), \
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val4, val5, val6, val7); \
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}
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|
|
#define LOAD_8VECS_SH(psrc, stride, \
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val0, val1, val2, val3, \
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val4, val5, val6, val7) \
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{ \
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LOAD_4VECS_SH((psrc), (stride), \
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val0, val1, val2, val3); \
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LOAD_4VECS_SH((psrc + 4 * stride), (stride), \
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val4, val5, val6, val7); \
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|
}
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|
|
|
#define LOAD_16VECS_SH(psrc, stride, \
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val0, val1, val2, val3, \
|
|
val4, val5, val6, val7, \
|
|
val8, val9, val10, val11, \
|
|
val12, val13, val14, val15) \
|
|
{ \
|
|
LOAD_8VECS_SH((psrc), (stride), \
|
|
val0, val1, val2, val3, \
|
|
val4, val5, val6, val7); \
|
|
LOAD_8VECS_SH((psrc + 8 * (stride)), (stride), \
|
|
val8, val9, val10, val11, \
|
|
val12, val13, val14, val15); \
|
|
}
|
|
|
|
#define STORE_4VECS_UB(dst_out, pitch, \
|
|
in0, in1, in2, in3) \
|
|
{ \
|
|
STORE_UB((in0), (dst_out)); \
|
|
STORE_UB((in1), ((dst_out) + (pitch))); \
|
|
STORE_UB((in2), ((dst_out) + 2 * (pitch))); \
|
|
STORE_UB((in3), ((dst_out) + 3 * (pitch))); \
|
|
}
|
|
|
|
#define STORE_4VECS_SB(dst_out, pitch, \
|
|
in0, in1, in2, in3) \
|
|
{ \
|
|
STORE_SB((in0), (dst_out)); \
|
|
STORE_SB((in1), ((dst_out) + (pitch))); \
|
|
STORE_SB((in2), ((dst_out) + 2 * (pitch))); \
|
|
STORE_SB((in3), ((dst_out) + 3 * (pitch))); \
|
|
}
|
|
|
|
#define STORE_8VECS_UB(dst_out, pitch_in, \
|
|
in0, in1, in2, in3, \
|
|
in4, in5, in6, in7) \
|
|
{ \
|
|
STORE_4VECS_UB(dst_out, pitch_in, \
|
|
in0, in1, in2, in3); \
|
|
STORE_4VECS_UB((dst_out + 4 * (pitch_in)), pitch_in, \
|
|
in4, in5, in6, in7); \
|
|
}
|
|
|
|
#define STORE_2VECS_SH(ptr, stride, \
|
|
in0, in1) \
|
|
{ \
|
|
STORE_SH(in0, ((ptr) + 0 * stride)); \
|
|
STORE_SH(in1, ((ptr) + 1 * stride)); \
|
|
}
|
|
|
|
#define STORE_4VECS_SH(ptr, stride, \
|
|
in0, in1, in2, in3) \
|
|
{ \
|
|
STORE_SH(in0, ((ptr) + 0 * stride)); \
|
|
STORE_SH(in1, ((ptr) + 1 * stride)); \
|
|
STORE_SH(in2, ((ptr) + 2 * stride)); \
|
|
STORE_SH(in3, ((ptr) + 3 * stride)); \
|
|
}
|
|
|
|
#define STORE_6VECS_SH(ptr, stride, \
|
|
in0, in1, in2, in3, \
|
|
in4, in5) \
|
|
{ \
|
|
STORE_SH(in0, ((ptr) + 0 * stride)); \
|
|
STORE_SH(in1, ((ptr) + 1 * stride)); \
|
|
STORE_SH(in2, ((ptr) + 2 * stride)); \
|
|
STORE_SH(in3, ((ptr) + 3 * stride)); \
|
|
STORE_SH(in4, ((ptr) + 4 * stride)); \
|
|
STORE_SH(in5, ((ptr) + 5 * stride)); \
|
|
}
|
|
|
|
#define STORE_8VECS_SH(ptr, stride, \
|
|
in0, in1, in2, in3, \
|
|
in4, in5, in6, in7) \
|
|
{ \
|
|
STORE_SH(in0, ((ptr) + 0 * stride)); \
|
|
STORE_SH(in1, ((ptr) + 1 * stride)); \
|
|
STORE_SH(in2, ((ptr) + 2 * stride)); \
|
|
STORE_SH(in3, ((ptr) + 3 * stride)); \
|
|
STORE_SH(in4, ((ptr) + 4 * stride)); \
|
|
STORE_SH(in5, ((ptr) + 5 * stride)); \
|
|
STORE_SH(in6, ((ptr) + 6 * stride)); \
|
|
STORE_SH(in7, ((ptr) + 7 * stride)); \
|
|
}
|
|
|
|
#define CLIP_MIN_TO_MAX_H(in, min, max) \
|
|
( { \
|
|
v8i16 out_m; \
|
|
\
|
|
out_m = __msa_max_s_h((v8i16) (min), (v8i16) (in)); \
|
|
out_m = __msa_min_s_h((v8i16) (max), (v8i16) out_m); \
|
|
out_m; \
|
|
} )
|
|
|
|
#define CLIP_UNSIGNED_CHAR_H(in) \
|
|
( { \
|
|
v8i16 max_m = __msa_ldi_h(255); \
|
|
v8i16 out_m; \
|
|
\
|
|
out_m = __msa_maxi_s_h((v8i16) (in), 0); \
|
|
out_m = __msa_min_s_h((v8i16) max_m, (v8i16) out_m); \
|
|
out_m; \
|
|
} )
|
|
|
|
#define CLIP_UNSIGNED_CHAR_W(in) \
|
|
( { \
|
|
v4i32 max_m = __msa_ldi_w(255); \
|
|
v4i32 out_m; \
|
|
\
|
|
out_m = __msa_maxi_s_w((v4i32) (in), 0); \
|
|
out_m = __msa_min_s_w((v4i32) max_m, (v4i32) out_m); \
|
|
out_m; \
|
|
} )
|
|
|
|
#define TRANSPOSE4x4_B_UB(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
v16i8 zero_m = { 0 }; \
|
|
v16i8 s0_m, s1_m, s2_m, s3_m; \
|
|
\
|
|
s0_m = (v16i8) __msa_ilvr_d((v2i64) (in1), (v2i64) (in0)); \
|
|
s1_m = (v16i8) __msa_ilvr_d((v2i64) (in3), (v2i64) (in2)); \
|
|
s2_m = __msa_ilvr_b(s1_m, s0_m); \
|
|
s3_m = __msa_ilvl_b(s1_m, s0_m); \
|
|
\
|
|
out0 = (v16u8) __msa_ilvr_b(s3_m, s2_m); \
|
|
out1 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out0, 4); \
|
|
out2 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out1, 4); \
|
|
out3 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out2, 4); \
|
|
}
|
|
|
|
#define TRANSPOSE8x4_B_UB(in0, in1, in2, in3, \
|
|
in4, in5, in6, in7, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
|
|
\
|
|
tmp0_m = (v16i8) __msa_ilvev_w((v4i32) (in4), (v4i32) (in0)); \
|
|
tmp1_m = (v16i8) __msa_ilvev_w((v4i32) (in5), (v4i32) (in1)); \
|
|
tmp2_m = __msa_ilvr_b(tmp1_m, tmp0_m); \
|
|
tmp0_m = (v16i8) __msa_ilvev_w((v4i32) (in6), (v4i32) (in2)); \
|
|
tmp1_m = (v16i8) __msa_ilvev_w((v4i32) (in7), (v4i32) (in3)); \
|
|
\
|
|
tmp3_m = __msa_ilvr_b(tmp1_m, tmp0_m); \
|
|
tmp0_m = (v16i8) __msa_ilvr_h((v8i16) tmp3_m, (v8i16) tmp2_m); \
|
|
tmp1_m = (v16i8) __msa_ilvl_h((v8i16) tmp3_m, (v8i16) tmp2_m); \
|
|
\
|
|
out0 = (v16u8) __msa_ilvr_w((v4i32) tmp1_m, (v4i32) tmp0_m); \
|
|
out2 = (v16u8) __msa_ilvl_w((v4i32) tmp1_m, (v4i32) tmp0_m); \
|
|
out1 = (v16u8) __msa_ilvl_d((v2i64) out2, (v2i64) out0); \
|
|
out3 = (v16u8) __msa_ilvl_d((v2i64) out0, (v2i64) out2); \
|
|
}
|
|
|
|
#define TRANSPOSE8x4_B_UH(in0, in1, in2, in3, \
|
|
in4, in5, in6, in7, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
|
|
\
|
|
tmp0_m = (v16i8) __msa_ilvev_w((v4i32) (in4), (v4i32) (in0)); \
|
|
tmp1_m = (v16i8) __msa_ilvev_w((v4i32) (in5), (v4i32) (in1)); \
|
|
tmp2_m = __msa_ilvr_b(tmp1_m, tmp0_m); \
|
|
tmp0_m = (v16i8) __msa_ilvev_w((v4i32) (in6), (v4i32) (in2)); \
|
|
tmp1_m = (v16i8) __msa_ilvev_w((v4i32) (in7), (v4i32) (in3)); \
|
|
\
|
|
tmp3_m = __msa_ilvr_b(tmp1_m, tmp0_m); \
|
|
tmp0_m = (v16i8) __msa_ilvr_h((v8i16) tmp3_m, (v8i16) tmp2_m); \
|
|
tmp1_m = (v16i8) __msa_ilvl_h((v8i16) tmp3_m, (v8i16) tmp2_m); \
|
|
\
|
|
out0 = (v8u16) __msa_ilvr_w((v4i32) tmp1_m, (v4i32) tmp0_m); \
|
|
out2 = (v8u16) __msa_ilvl_w((v4i32) tmp1_m, (v4i32) tmp0_m); \
|
|
out1 = (v8u16) __msa_ilvl_d((v2i64) out2, (v2i64) out0); \
|
|
out3 = (v8u16) __msa_ilvl_d((v2i64) out0, (v2i64) out2); \
|
|
}
|
|
|
|
#define TRANSPOSE8x8_B_UB(in0, in1, in2, in3, \
|
|
in4, in5, in6, in7, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
|
|
v16i8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
|
|
v16i8 zero_m = { 0 }; \
|
|
\
|
|
tmp0_m = __msa_ilvr_b((v16i8) (in2), (v16i8) (in0)); \
|
|
tmp1_m = __msa_ilvr_b((v16i8) (in3), (v16i8) (in1)); \
|
|
tmp2_m = __msa_ilvr_b((v16i8) (in6), (v16i8) (in4)); \
|
|
tmp3_m = __msa_ilvr_b((v16i8) (in7), (v16i8) (in5)); \
|
|
\
|
|
tmp4_m = __msa_ilvr_b((v16i8) tmp1_m, (v16i8) tmp0_m); \
|
|
tmp5_m = __msa_ilvl_b((v16i8) tmp1_m, (v16i8) tmp0_m); \
|
|
tmp6_m = __msa_ilvr_b((v16i8) tmp3_m, (v16i8) tmp2_m); \
|
|
tmp7_m = __msa_ilvl_b((v16i8) tmp3_m, (v16i8) tmp2_m); \
|
|
\
|
|
out0 = (v16u8) __msa_ilvr_w((v4i32) tmp6_m, (v4i32) tmp4_m); \
|
|
out2 = (v16u8) __msa_ilvl_w((v4i32) tmp6_m, (v4i32) tmp4_m); \
|
|
out4 = (v16u8) __msa_ilvr_w((v4i32) tmp7_m, (v4i32) tmp5_m); \
|
|
out6 = (v16u8) __msa_ilvl_w((v4i32) tmp7_m, (v4i32) tmp5_m); \
|
|
\
|
|
out1 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out0, 8); \
|
|
out3 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out2, 8); \
|
|
out5 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out4, 8); \
|
|
out7 = (v16u8) __msa_sldi_b(zero_m, (v16i8) out6, 8); \
|
|
}
|
|
|
|
#define TRANSPOSE8x8_B_UH(in0, in1, in2, in3, \
|
|
in4, in5, in6, in7, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
|
|
v16i8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
|
|
v16i8 zero_m = { 0 }; \
|
|
\
|
|
tmp0_m = __msa_ilvr_b((v16i8) (in2), (v16i8) (in0)); \
|
|
tmp1_m = __msa_ilvr_b((v16i8) (in3), (v16i8) (in1)); \
|
|
tmp2_m = __msa_ilvr_b((v16i8) (in6), (v16i8) (in4)); \
|
|
tmp3_m = __msa_ilvr_b((v16i8) (in7), (v16i8) (in5)); \
|
|
\
|
|
tmp4_m = __msa_ilvr_b((v16i8) tmp1_m, (v16i8) tmp0_m); \
|
|
tmp5_m = __msa_ilvl_b((v16i8) tmp1_m, (v16i8) tmp0_m); \
|
|
tmp6_m = __msa_ilvr_b((v16i8) tmp3_m, (v16i8) tmp2_m); \
|
|
tmp7_m = __msa_ilvl_b((v16i8) tmp3_m, (v16i8) tmp2_m); \
|
|
\
|
|
out0 = (v8u16) __msa_ilvr_w((v4i32) tmp6_m, (v4i32) tmp4_m); \
|
|
out2 = (v8u16) __msa_ilvl_w((v4i32) tmp6_m, (v4i32) tmp4_m); \
|
|
out4 = (v8u16) __msa_ilvr_w((v4i32) tmp7_m, (v4i32) tmp5_m); \
|
|
out6 = (v8u16) __msa_ilvl_w((v4i32) tmp7_m, (v4i32) tmp5_m); \
|
|
out1 = (v8u16) __msa_sldi_b(zero_m, (v16i8) out0, 8); \
|
|
out3 = (v8u16) __msa_sldi_b(zero_m, (v16i8) out2, 8); \
|
|
out5 = (v8u16) __msa_sldi_b(zero_m, (v16i8) out4, 8); \
|
|
out7 = (v8u16) __msa_sldi_b(zero_m, (v16i8) out6, 8); \
|
|
}
|
|
|
|
#define TRANSPOSE16x8_B_UB(in0, in1, in2, in3, \
|
|
in4, in5, in6, in7, \
|
|
in8, in9, in10, in11, \
|
|
in12, in13, in14, in15, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
|
|
v16u8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
|
|
\
|
|
(out7) = (v16u8) __msa_ilvev_d((v2i64) (in8), (v2i64) (in0)); \
|
|
(out6) = (v16u8) __msa_ilvev_d((v2i64) (in9), (v2i64) (in1)); \
|
|
(out5) = (v16u8) __msa_ilvev_d((v2i64) (in10), (v2i64) (in2)); \
|
|
(out4) = (v16u8) __msa_ilvev_d((v2i64) (in11), (v2i64) (in3)); \
|
|
(out3) = (v16u8) __msa_ilvev_d((v2i64) (in12), (v2i64) (in4)); \
|
|
(out2) = (v16u8) __msa_ilvev_d((v2i64) (in13), (v2i64) (in5)); \
|
|
(out1) = (v16u8) __msa_ilvev_d((v2i64) (in14), (v2i64) (in6)); \
|
|
(out0) = (v16u8) __msa_ilvev_d((v2i64) (in15), (v2i64) (in7)); \
|
|
\
|
|
tmp0_m = (v16u8) __msa_ilvev_b((v16i8) (out6), (v16i8) (out7)); \
|
|
tmp4_m = (v16u8) __msa_ilvod_b((v16i8) (out6), (v16i8) (out7)); \
|
|
tmp1_m = (v16u8) __msa_ilvev_b((v16i8) (out4), (v16i8) (out5)); \
|
|
tmp5_m = (v16u8) __msa_ilvod_b((v16i8) (out4), (v16i8) (out5)); \
|
|
(out5) = (v16u8) __msa_ilvev_b((v16i8) (out2), (v16i8) (out3)); \
|
|
tmp6_m = (v16u8) __msa_ilvod_b((v16i8) (out2), (v16i8) (out3)); \
|
|
(out7) = (v16u8) __msa_ilvev_b((v16i8) (out0), (v16i8) (out1)); \
|
|
tmp7_m = (v16u8) __msa_ilvod_b((v16i8) (out0), (v16i8) (out1)); \
|
|
\
|
|
tmp2_m = (v16u8) __msa_ilvev_h((v8i16) tmp1_m, (v8i16) tmp0_m); \
|
|
tmp3_m = (v16u8) __msa_ilvev_h((v8i16) (out7), (v8i16) (out5)); \
|
|
(out0) = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
(out4) = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
\
|
|
tmp2_m = (v16u8) __msa_ilvod_h((v8i16) tmp1_m, (v8i16) tmp0_m); \
|
|
tmp3_m = (v16u8) __msa_ilvod_h((v8i16) (out7), (v8i16) (out5)); \
|
|
(out2) = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
(out6) = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
\
|
|
tmp2_m = (v16u8) __msa_ilvev_h((v8i16) tmp5_m, (v8i16) tmp4_m); \
|
|
tmp3_m = (v16u8) __msa_ilvev_h((v8i16) tmp7_m, (v8i16) tmp6_m); \
|
|
(out1) = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
(out5) = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
\
|
|
tmp2_m = (v16u8) __msa_ilvod_h((v8i16) tmp5_m, (v8i16) tmp4_m); \
|
|
tmp2_m = (v16u8) __msa_ilvod_h((v8i16) tmp5_m, (v8i16) tmp4_m); \
|
|
tmp3_m = (v16u8) __msa_ilvod_h((v8i16) tmp7_m, (v8i16) tmp6_m); \
|
|
tmp3_m = (v16u8) __msa_ilvod_h((v8i16) tmp7_m, (v8i16) tmp6_m); \
|
|
(out3) = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
(out7) = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
|
|
}
|
|
|
|
#define TRANSPOSE8x8_H_SH(in0, in1, in2, in3, \
|
|
in4, in5, in6, in7, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
v8i16 s0_m, s1_m; \
|
|
v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
|
|
v8i16 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
|
|
\
|
|
s0_m = __msa_ilvr_h((v8i16) (in6), (v8i16) (in4)); \
|
|
s1_m = __msa_ilvr_h((v8i16) (in7), (v8i16) (in5)); \
|
|
tmp0_m = __msa_ilvr_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
tmp1_m = __msa_ilvl_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
\
|
|
s0_m = __msa_ilvl_h((v8i16) (in6), (v8i16) (in4)); \
|
|
s1_m = __msa_ilvl_h((v8i16) (in7), (v8i16) (in5)); \
|
|
tmp2_m = __msa_ilvr_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
tmp3_m = __msa_ilvl_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
\
|
|
s0_m = __msa_ilvr_h((v8i16) (in2), (v8i16) (in0)); \
|
|
s1_m = __msa_ilvr_h((v8i16) (in3), (v8i16) (in1)); \
|
|
tmp4_m = __msa_ilvr_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
tmp5_m = __msa_ilvl_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
\
|
|
s0_m = __msa_ilvl_h((v8i16) (in2), (v8i16) (in0)); \
|
|
s1_m = __msa_ilvl_h((v8i16) (in3), (v8i16) (in1)); \
|
|
tmp6_m = __msa_ilvr_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
tmp7_m = __msa_ilvl_h((v8i16) s1_m, (v8i16) s0_m); \
|
|
\
|
|
out0 = (v8i16) __msa_pckev_d((v2i64) tmp0_m, (v2i64) tmp4_m); \
|
|
out1 = (v8i16) __msa_pckod_d((v2i64) tmp0_m, (v2i64) tmp4_m); \
|
|
out2 = (v8i16) __msa_pckev_d((v2i64) tmp1_m, (v2i64) tmp5_m); \
|
|
out3 = (v8i16) __msa_pckod_d((v2i64) tmp1_m, (v2i64) tmp5_m); \
|
|
out4 = (v8i16) __msa_pckev_d((v2i64) tmp2_m, (v2i64) tmp6_m); \
|
|
out5 = (v8i16) __msa_pckod_d((v2i64) tmp2_m, (v2i64) tmp6_m); \
|
|
out6 = (v8i16) __msa_pckev_d((v2i64) tmp3_m, (v2i64) tmp7_m); \
|
|
out7 = (v8i16) __msa_pckod_d((v2i64) tmp3_m, (v2i64) tmp7_m); \
|
|
}
|
|
|
|
#define TRANSPOSE4x4_W(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
v4i32 s0_m, s1_m, s2_m, s3_m; \
|
|
\
|
|
s0_m = __msa_ilvr_w((v4i32) (in1), (v4i32) (in0)); \
|
|
s1_m = __msa_ilvl_w((v4i32) (in1), (v4i32) (in0)); \
|
|
s2_m = __msa_ilvr_w((v4i32) (in3), (v4i32) (in2)); \
|
|
s3_m = __msa_ilvl_w((v4i32) (in3), (v4i32) (in2)); \
|
|
\
|
|
out0 = (v4i32) __msa_ilvr_d((v2i64) s2_m, (v2i64) s0_m); \
|
|
out1 = (v4i32) __msa_ilvl_d((v2i64) s2_m, (v2i64) s0_m); \
|
|
out2 = (v4i32) __msa_ilvr_d((v2i64) s3_m, (v2i64) s1_m); \
|
|
out3 = (v4i32) __msa_ilvl_d((v2i64) s3_m, (v2i64) s1_m); \
|
|
}
|
|
|
|
#define ILV_B_LRLR_SB(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = __msa_ilvl_b((v16i8) (in1), (v16i8) (in0)); \
|
|
out1 = __msa_ilvr_b((v16i8) (in1), (v16i8) (in0)); \
|
|
out2 = __msa_ilvl_b((v16i8) (in3), (v16i8) (in2)); \
|
|
out3 = __msa_ilvr_b((v16i8) (in3), (v16i8) (in2)); \
|
|
}
|
|
|
|
#define ILV_B_LRLR_UH(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = (v8u16) __msa_ilvl_b((v16i8) (in1), (v16i8) (in0)); \
|
|
out1 = (v8u16) __msa_ilvr_b((v16i8) (in1), (v16i8) (in0)); \
|
|
out2 = (v8u16) __msa_ilvl_b((v16i8) (in3), (v16i8) (in2)); \
|
|
out3 = (v8u16) __msa_ilvr_b((v16i8) (in3), (v16i8) (in2)); \
|
|
}
|
|
|
|
#define ILV_B_LRLR_SH(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = (v8i16) __msa_ilvl_b((v16i8) (in1), (v16i8) (in0)); \
|
|
out1 = (v8i16) __msa_ilvr_b((v16i8) (in1), (v16i8) (in0)); \
|
|
out2 = (v8i16) __msa_ilvl_b((v16i8) (in3), (v16i8) (in2)); \
|
|
out3 = (v8i16) __msa_ilvr_b((v16i8) (in3), (v16i8) (in2)); \
|
|
}
|
|
|
|
#define ILV_H_LRLR_SW(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = (v4i32) __msa_ilvl_h((v8i16) (in1), (v8i16) (in0)); \
|
|
out1 = (v4i32) __msa_ilvr_h((v8i16) (in1), (v8i16) (in0)); \
|
|
out2 = (v4i32) __msa_ilvl_h((v8i16) (in3), (v8i16) (in2)); \
|
|
out3 = (v4i32) __msa_ilvr_h((v8i16) (in3), (v8i16) (in2)); \
|
|
}
|
|
|
|
#define ILVR_B_2VECS_UB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = (v16u8) __msa_ilvr_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = (v16u8) __msa_ilvr_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
}
|
|
|
|
#define ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = __msa_ilvr_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = __msa_ilvr_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
}
|
|
|
|
#define ILVR_B_4VECS_SB(in0_r, in1_r, in2_r, in3_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
}
|
|
|
|
#define ILVR_B_6VECS_SB(in0_r, in1_r, in2_r, \
|
|
in3_r, in4_r, in5_r, \
|
|
in0_l, in1_l, in2_l, \
|
|
in3_l, in4_l, in5_l, \
|
|
out0, out1, out2, \
|
|
out3, out4, out5) \
|
|
{ \
|
|
ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVR_B_2VECS_SB(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
}
|
|
|
|
#define ILVR_B_8VECS_SB(in0_r, in1_r, in2_r, in3_r, \
|
|
in4_r, in5_r, in6_r, in7_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
in4_l, in5_l, in6_l, in7_l, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVR_B_2VECS_SB(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
ILVR_B_2VECS_SB(in6_r, in7_r, in6_l, in7_l, \
|
|
out6, out7); \
|
|
}
|
|
|
|
#define ILVR_B_2VECS_UH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = (v8u16) __msa_ilvr_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = (v8u16) __msa_ilvr_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
}
|
|
|
|
#define ILVR_B_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = (v8i16) __msa_ilvr_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = (v8i16) __msa_ilvr_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
}
|
|
|
|
#define ILVR_B_3VECS_SH(in0_r, in1_r, in2_r, in0_l, in1_l, in2_l, \
|
|
out0, out1, out2) \
|
|
{ \
|
|
ILVR_B_2VECS_SH(in0_r, in1_r, in0_l, in1_l, out0, out1); \
|
|
out2 = (v8i16) __msa_ilvr_b((v16i8) (in2_l), (v16i8) (in2_r)); \
|
|
}
|
|
|
|
#define ILVR_B_4VECS_UH(in0_r, in1_r, in2_r, in3_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
ILVR_B_2VECS_UH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_B_2VECS_UH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
}
|
|
|
|
#define ILVR_B_4VECS_SH(in0_r, in1_r, in2_r, in3_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
ILVR_B_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_B_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
}
|
|
|
|
#define ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = __msa_ilvr_h((v8i16) (in0_l), (v8i16) (in0_r)); \
|
|
out1 = __msa_ilvr_h((v8i16) (in1_l), (v8i16) (in1_r)); \
|
|
}
|
|
|
|
#define ILVR_H_4VECS_SH(in0_r, in1_r, in2_r, in3_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
}
|
|
|
|
#define ILVR_H_6VECS_SH(in0_r, in1_r, in2_r, \
|
|
in3_r, in4_r, in5_r, \
|
|
in0_l, in1_l, in2_l, \
|
|
in3_l, in4_l, in5_l, \
|
|
out0, out1, out2, \
|
|
out3, out4, out5) \
|
|
{ \
|
|
ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVR_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
}
|
|
|
|
#define ILVR_H_8VECS_SH(in0_r, in1_r, in2_r, in3_r, \
|
|
in4_r, in5_r, in6_r, in7_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
in4_l, in5_l, in6_l, in7_l, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVR_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVR_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
ILVR_H_2VECS_SH(in6_r, in7_r, in6_l, in7_l, \
|
|
out6, out7); \
|
|
}
|
|
|
|
#define ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = __msa_ilvl_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = __msa_ilvl_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
}
|
|
|
|
#define ILVL_B_4VECS_SB(in0_r, in1_r, in2_r, in3_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVL_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
}
|
|
|
|
#define ILVL_B_6VECS_SB(in0_r, in1_r, in2_r, \
|
|
in3_r, in4_r, in5_r, \
|
|
in0_l, in1_l, in2_l, \
|
|
in3_l, in4_l, in5_l, \
|
|
out0, out1, out2, \
|
|
out3, out4, out5) \
|
|
{ \
|
|
ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVL_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVL_B_2VECS_SB(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
}
|
|
|
|
#define ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1) \
|
|
{ \
|
|
out0 = __msa_ilvl_h((v8i16) (in0_l), (v8i16) (in0_r)); \
|
|
out1 = __msa_ilvl_h((v8i16) (in1_l), (v8i16) (in1_r)); \
|
|
}
|
|
|
|
#define ILVL_H_4VECS_SH(in0_r, in1_r, in2_r, in3_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVL_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
}
|
|
|
|
#define ILVL_H_6VECS_SH(in0_r, in1_r, in2_r, \
|
|
in3_r, in4_r, in5_r, \
|
|
in0_l, in1_l, in2_l, \
|
|
in3_l, in4_l, in5_l, \
|
|
out0, out1, out2, \
|
|
out3, out4, out5) \
|
|
{ \
|
|
ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVL_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVL_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
}
|
|
|
|
#define ILVL_H_8VECS_SH(in0_r, in1_r, in2_r, in3_r, \
|
|
in4_r, in5_r, in6_r, in7_r, \
|
|
in0_l, in1_l, in2_l, in3_l, \
|
|
in4_l, in5_l, in6_l, in7_l, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7) \
|
|
{ \
|
|
ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
|
|
out0, out1); \
|
|
ILVL_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
|
|
out2, out3); \
|
|
ILVL_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
|
|
out4, out5); \
|
|
ILVL_H_2VECS_SH(in6_r, in7_r, in6_l, in7_l, \
|
|
out6, out7); \
|
|
}
|
|
|
|
#define ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
|
|
out1, in1_l, in1_r) \
|
|
{ \
|
|
out0 = (v16i8) __msa_ilvr_d((v2i64) (in0_l), (v2i64) (in0_r)); \
|
|
out1 = (v16i8) __msa_ilvr_d((v2i64) (in1_l), (v2i64) (in1_r)); \
|
|
}
|
|
|
|
#define ILVR_D_3VECS_SB(out0, in0_l, in0_r, \
|
|
out1, in1_l, in1_r, \
|
|
out2, in2_l, in2_r) \
|
|
{ \
|
|
ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
|
|
out1, in1_l, in1_r); \
|
|
out2 = (v16i8) __msa_ilvr_d((v2i64) (in2_l), (v2i64) (in2_r)); \
|
|
}
|
|
|
|
#define ILVR_D_4VECS_SB(out0, in0_l, in0_r, \
|
|
out1, in1_l, in1_r, \
|
|
out2, in2_l, in2_r, \
|
|
out3, in3_l, in3_r) \
|
|
{ \
|
|
ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
|
|
out1, in1_l, in1_r); \
|
|
ILVR_D_2VECS_SB(out2, in2_l, in2_r, \
|
|
out3, in3_l, in3_r); \
|
|
}
|
|
|
|
#define MAXI_S_H_4VECS_UH(vec0, vec1, vec2, vec3, max_value) \
|
|
{ \
|
|
vec0 = (v8u16) __msa_maxi_s_h((v8i16) (vec0), (max_value)); \
|
|
vec1 = (v8u16) __msa_maxi_s_h((v8i16) (vec1), (max_value)); \
|
|
vec2 = (v8u16) __msa_maxi_s_h((v8i16) (vec2), (max_value)); \
|
|
vec3 = (v8u16) __msa_maxi_s_h((v8i16) (vec3), (max_value)); \
|
|
}
|
|
|
|
#define SAT_U_H_4VECS_UH(vec0, vec1, vec2, vec3, sat_value) \
|
|
{ \
|
|
vec0 = __msa_sat_u_h((v8u16) (vec0), (sat_value)); \
|
|
vec1 = __msa_sat_u_h((v8u16) (vec1), (sat_value)); \
|
|
vec2 = __msa_sat_u_h((v8u16) (vec2), (sat_value)); \
|
|
vec3 = __msa_sat_u_h((v8u16) (vec3), (sat_value)); \
|
|
}
|
|
|
|
#define PCKEV_B_4VECS_UB(in0_l, in1_l, in2_l, in3_l, \
|
|
in0_r, in1_r, in2_r, in3_r, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = (v16u8) __msa_pckev_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = (v16u8) __msa_pckev_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
out2 = (v16u8) __msa_pckev_b((v16i8) (in2_l), (v16i8) (in2_r)); \
|
|
out3 = (v16u8) __msa_pckev_b((v16i8) (in3_l), (v16i8) (in3_r)); \
|
|
}
|
|
|
|
#define PCKEV_B_4VECS_SB(in0_l, in1_l, in2_l, in3_l, \
|
|
in0_r, in1_r, in2_r, in3_r, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = __msa_pckev_b((v16i8) (in0_l), (v16i8) (in0_r)); \
|
|
out1 = __msa_pckev_b((v16i8) (in1_l), (v16i8) (in1_r)); \
|
|
out2 = __msa_pckev_b((v16i8) (in2_l), (v16i8) (in2_r)); \
|
|
out3 = __msa_pckev_b((v16i8) (in3_l), (v16i8) (in3_r)); \
|
|
}
|
|
|
|
#define XORI_B_2VECS_UB(val0, val1, out0, out1, xor_val) \
|
|
{ \
|
|
out0 = __msa_xori_b((v16u8) (val0), (xor_val)); \
|
|
out1 = __msa_xori_b((v16u8) (val1), (xor_val)); \
|
|
}
|
|
|
|
#define XORI_B_2VECS_SB(val0, val1, \
|
|
out0, out1, xor_val) \
|
|
{ \
|
|
out0 = (v16i8) __msa_xori_b((v16u8) (val0), (xor_val)); \
|
|
out1 = (v16i8) __msa_xori_b((v16u8) (val1), (xor_val)); \
|
|
}
|
|
|
|
#define XORI_B_3VECS_SB(val0, val1, val2, \
|
|
out0, out1, out2, \
|
|
xor_val) \
|
|
{ \
|
|
XORI_B_2VECS_SB(val0, val1, \
|
|
out0, out1, xor_val); \
|
|
out2 = (v16i8) __msa_xori_b((v16u8) (val2), (xor_val)); \
|
|
}
|
|
|
|
#define XORI_B_4VECS_UB(val0, val1, val2, val3, \
|
|
out0, out1, out2, out3, xor_val) \
|
|
{ \
|
|
XORI_B_2VECS_UB(val0, val1, out0, out1, xor_val); \
|
|
XORI_B_2VECS_UB(val2, val3, out2, out3, xor_val); \
|
|
}
|
|
|
|
#define XORI_B_4VECS_SB(val0, val1, val2, val3, \
|
|
out0, out1, out2, out3, \
|
|
xor_val) \
|
|
{ \
|
|
XORI_B_2VECS_SB(val0, val1, \
|
|
out0, out1, xor_val); \
|
|
XORI_B_2VECS_SB(val2, val3, \
|
|
out2, out3, xor_val); \
|
|
}
|
|
|
|
#define XORI_B_5VECS_SB(val0, val1, val2, val3, val4, \
|
|
out0, out1, out2, out3, out4, \
|
|
xor_val) \
|
|
{ \
|
|
XORI_B_3VECS_SB(val0, val1, val2, \
|
|
out0, out1, out2, xor_val); \
|
|
XORI_B_2VECS_SB(val3, val4, \
|
|
out3, out4, xor_val); \
|
|
}
|
|
|
|
#define XORI_B_6VECS_SB(val0, val1, val2, val3, val4, val5, \
|
|
out0, out1, out2, out3, out4, out5, \
|
|
xor_val) \
|
|
{ \
|
|
XORI_B_4VECS_SB(val0, val1, val2, val3, \
|
|
out0, out1, out2, out3, xor_val); \
|
|
XORI_B_2VECS_SB(val4, val5,out4, out5, xor_val); \
|
|
}
|
|
|
|
#define XORI_B_7VECS_SB(val0, val1, val2, val3, \
|
|
val4, val5, val6, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, \
|
|
xor_val) \
|
|
{ \
|
|
XORI_B_4VECS_SB(val0, val1, val2, val3, \
|
|
out0, out1, out2, out3, xor_val); \
|
|
XORI_B_3VECS_SB(val4, val5, val6, \
|
|
out4, out5, out6, xor_val); \
|
|
}
|
|
|
|
#define XORI_B_8VECS_SB(val0, val1, val2, val3, \
|
|
val4, val5, val6, val7, \
|
|
out0, out1, out2, out3, \
|
|
out4, out5, out6, out7, xor_val) \
|
|
{ \
|
|
XORI_B_4VECS_SB(val0, val1, val2, val3, \
|
|
out0, out1, out2, out3, xor_val); \
|
|
XORI_B_4VECS_SB(val4, val5, val6, val7, \
|
|
out4, out5, out6, out7, xor_val); \
|
|
}
|
|
#define ADDS_S_H_4VECS_UH(in0, in1, in2, in3, in4, in5, in6, in7, \
|
|
out0, out1, out2, out3) \
|
|
{ \
|
|
out0 = (v8u16) __msa_adds_s_h((v8i16) (in0), (v8i16) (in1)); \
|
|
out1 = (v8u16) __msa_adds_s_h((v8i16) (in2), (v8i16) (in3)); \
|
|
out2 = (v8u16) __msa_adds_s_h((v8i16) (in4), (v8i16) (in5)); \
|
|
out3 = (v8u16) __msa_adds_s_h((v8i16) (in6), (v8i16) (in7)); \
|
|
}
|
|
#define SRA_4VECS(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3, \
|
|
shift_right_vec) \
|
|
{ \
|
|
out0 = (in0) >> (shift_right_vec); \
|
|
out1 = (in1) >> (shift_right_vec); \
|
|
out2 = (in2) >> (shift_right_vec); \
|
|
out3 = (in3) >> (shift_right_vec); \
|
|
}
|
|
|
|
#define SRL_H_4VECS_UH(in0, in1, in2, in3, \
|
|
out0, out1, out2, out3, \
|
|
shift_right_vec) \
|
|
{ \
|
|
out0 = (v8u16) __msa_srl_h((v8i16) (in0), (v8i16) (shift_right_vec)); \
|
|
out1 = (v8u16) __msa_srl_h((v8i16) (in1), (v8i16) (shift_right_vec)); \
|
|
out2 = (v8u16) __msa_srl_h((v8i16) (in2), (v8i16) (shift_right_vec)); \
|
|
out3 = (v8u16) __msa_srl_h((v8i16) (in3), (v8i16) (shift_right_vec)); \
|
|
}
|
|
|
|
#define SRAR_SATURATE_SIGNED_H(input, right_shift_vec, sat_val) \
|
|
( { \
|
|
v8i16 out_m; \
|
|
\
|
|
out_m = __msa_srar_h((v8i16) (input), (v8i16) (right_shift_vec)); \
|
|
out_m = __msa_sat_s_h(out_m, (sat_val)); \
|
|
out_m; \
|
|
} )
|
|
|
|
#define PCKEV_2B_XORI128_STORE_4_BYTES_4(in1, in2, \
|
|
pdst, stride) \
|
|
{ \
|
|
uint32_t out0_m, out1_m, out2_m, out3_m; \
|
|
v16i8 tmp0_m; \
|
|
uint8_t *dst_m = (uint8_t *) (pdst); \
|
|
\
|
|
tmp0_m = __msa_pckev_b((v16i8) (in2), (v16i8) (in1)); \
|
|
tmp0_m = (v16i8) __msa_xori_b((v16u8) tmp0_m, 128); \
|
|
\
|
|
out0_m = __msa_copy_u_w((v4i32) tmp0_m, 0); \
|
|
out1_m = __msa_copy_u_w((v4i32) tmp0_m, 1); \
|
|
out2_m = __msa_copy_u_w((v4i32) tmp0_m, 2); \
|
|
out3_m = __msa_copy_u_w((v4i32) tmp0_m, 3); \
|
|
\
|
|
STORE_WORD(dst_m, out0_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out1_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out2_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out3_m); \
|
|
}
|
|
|
|
#define PCKEV_B_XORI128_STORE_8_BYTES(in1, in2, pdest) \
|
|
{ \
|
|
uint64_t out_m; \
|
|
v16i8 tmp_m; \
|
|
\
|
|
tmp_m = __msa_pckev_b((v16i8) (in1), (v16i8) (in2)); \
|
|
tmp_m = (v16i8) __msa_xori_b((v16u8) tmp_m, 128); \
|
|
out_m = __msa_copy_u_d((v2i64) tmp_m, 0); \
|
|
STORE_DWORD((pdest), out_m); \
|
|
}
|
|
|
|
#define PCKEV_B_XORI128_STORE_8_BYTES_2(in1, in2, \
|
|
pdst, stride) \
|
|
{ \
|
|
uint64_t out0_m, out1_m; \
|
|
v16i8 tmp0_m; \
|
|
uint8_t *dst_m = (uint8_t *) (pdst); \
|
|
\
|
|
tmp0_m = __msa_pckev_b((v16i8) (in2), (v16i8) (in1)); \
|
|
tmp0_m = (v16i8) __msa_xori_b((v16u8) tmp0_m, 128); \
|
|
\
|
|
out0_m = __msa_copy_u_d((v2i64) tmp0_m, 0); \
|
|
out1_m = __msa_copy_u_d((v2i64) tmp0_m, 1); \
|
|
\
|
|
STORE_DWORD(dst_m, out0_m); \
|
|
dst_m += stride; \
|
|
STORE_DWORD(dst_m, out1_m); \
|
|
}
|
|
|
|
#define PCKEV_B_XORI128_STORE_6_BYTES_4(in1, in2, in3, in4, \
|
|
pdst, stride) \
|
|
{ \
|
|
uint32_t out0_m, out1_m, out2_m, out3_m; \
|
|
uint16_t out4_m, out5_m, out6_m, out7_m; \
|
|
v16i8 tmp0_m, tmp1_m; \
|
|
uint8_t *dst_m = (uint8_t *) (pdst); \
|
|
\
|
|
tmp0_m = __msa_pckev_b((v16i8) (in2), (v16i8) (in1)); \
|
|
tmp1_m = __msa_pckev_b((v16i8) (in4), (v16i8) (in3)); \
|
|
\
|
|
tmp0_m = (v16i8) __msa_xori_b((v16u8) tmp0_m, 128); \
|
|
tmp1_m = (v16i8) __msa_xori_b((v16u8) tmp1_m, 128); \
|
|
\
|
|
out0_m = __msa_copy_u_w((v4i32) tmp0_m, 0); \
|
|
out1_m = __msa_copy_u_w((v4i32) tmp0_m, 2); \
|
|
out2_m = __msa_copy_u_w((v4i32) tmp1_m, 0); \
|
|
out3_m = __msa_copy_u_w((v4i32) tmp1_m, 2); \
|
|
\
|
|
out4_m = __msa_copy_u_h((v8i16) tmp0_m, 2); \
|
|
out5_m = __msa_copy_u_h((v8i16) tmp0_m, 6); \
|
|
out6_m = __msa_copy_u_h((v8i16) tmp1_m, 2); \
|
|
out7_m = __msa_copy_u_h((v8i16) tmp1_m, 6); \
|
|
\
|
|
STORE_WORD(dst_m, out0_m); \
|
|
STORE_HWORD((dst_m + 4), out4_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out1_m); \
|
|
STORE_HWORD((dst_m + 4), out5_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out2_m); \
|
|
STORE_HWORD((dst_m + 4), out6_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out3_m); \
|
|
STORE_HWORD((dst_m + 4), out7_m); \
|
|
}
|
|
|
|
#define PCKEV_B_4_XORI128_STORE_8_BYTES_4(in1, in2, in3, in4, \
|
|
pdst, stride) \
|
|
{ \
|
|
uint64_t out0_m, out1_m, out2_m, out3_m; \
|
|
v16i8 tmp0_m, tmp1_m; \
|
|
uint8_t *dst_m = (uint8_t *) (pdst); \
|
|
\
|
|
tmp0_m = __msa_pckev_b((v16i8) (in2), (v16i8) (in1)); \
|
|
tmp1_m = __msa_pckev_b((v16i8) (in4), (v16i8) (in3)); \
|
|
\
|
|
tmp0_m = (v16i8) __msa_xori_b((v16u8) tmp0_m, 128); \
|
|
tmp1_m = (v16i8) __msa_xori_b((v16u8) tmp1_m, 128); \
|
|
\
|
|
out0_m = __msa_copy_u_d((v2i64) tmp0_m, 0); \
|
|
out1_m = __msa_copy_u_d((v2i64) tmp0_m, 1); \
|
|
out2_m = __msa_copy_u_d((v2i64) tmp1_m, 0); \
|
|
out3_m = __msa_copy_u_d((v2i64) tmp1_m, 1); \
|
|
\
|
|
STORE_DWORD(dst_m, out0_m); \
|
|
dst_m += stride; \
|
|
STORE_DWORD(dst_m, out1_m); \
|
|
dst_m += stride; \
|
|
STORE_DWORD(dst_m, out2_m); \
|
|
dst_m += stride; \
|
|
STORE_DWORD(dst_m, out3_m); \
|
|
}
|
|
#define PCKEV_B_XORI128_STORE_VEC(in1, in2, pdest) \
|
|
{ \
|
|
v16i8 tmp_m; \
|
|
\
|
|
tmp_m = __msa_pckev_b((v16i8) (in1), (v16i8) (in2)); \
|
|
tmp_m = (v16i8) __msa_xori_b((v16u8) tmp_m, 128); \
|
|
STORE_SB(tmp_m, (pdest)); \
|
|
}
|
|
|
|
#define PCKEV_B_STORE_4_BYTES_4(in1, in2, in3, in4, \
|
|
pdst, stride) \
|
|
{ \
|
|
uint32_t out0_m, out1_m, out2_m, out3_m; \
|
|
v16i8 tmp0_m, tmp1_m; \
|
|
uint8_t *dst_m = (uint8_t *) (pdst); \
|
|
\
|
|
tmp0_m = __msa_pckev_b((v16i8) (in2), (v16i8) (in1)); \
|
|
tmp1_m = __msa_pckev_b((v16i8) (in4), (v16i8) (in3)); \
|
|
\
|
|
out0_m = __msa_copy_u_w((v4i32) tmp0_m, 0); \
|
|
out1_m = __msa_copy_u_w((v4i32) tmp0_m, 2); \
|
|
out2_m = __msa_copy_u_w((v4i32) tmp1_m, 0); \
|
|
out3_m = __msa_copy_u_w((v4i32) tmp1_m, 2); \
|
|
\
|
|
STORE_WORD(dst_m, out0_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out1_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out2_m); \
|
|
dst_m += stride; \
|
|
STORE_WORD(dst_m, out3_m); \
|
|
}
|
|
|
|
#define PCKEV_B_STORE_8_BYTES_4(in1, in2, in3, in4, \
|
|
pdst, stride) \
|
|
{ \
|
|
uint64_t out0_m, out1_m, out2_m, out3_m; \
|
|
v16i8 tmp0_m, tmp1_m; \
|
|
uint8_t *dst_m = (uint8_t *) (pdst); \
|
|
\
|
|
tmp0_m = __msa_pckev_b((v16i8) (in2), (v16i8) (in1)); \
|
|
tmp1_m = __msa_pckev_b((v16i8) (in4), (v16i8) (in3)); \
|
|
\
|
|
out0_m = __msa_copy_u_d((v2i64) tmp0_m, 0); \
|
|
out1_m = __msa_copy_u_d((v2i64) tmp0_m, 1); \
|
|
out2_m = __msa_copy_u_d((v2i64) tmp1_m, 0); \
|
|
out3_m = __msa_copy_u_d((v2i64) tmp1_m, 1); \
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\
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STORE_DWORD(dst_m, out0_m); \
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dst_m += stride; \
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STORE_DWORD(dst_m, out1_m); \
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dst_m += stride; \
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STORE_DWORD(dst_m, out2_m); \
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dst_m += stride; \
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STORE_DWORD(dst_m, out3_m); \
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}
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|
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#define UNPCK_SIGNED_B_TO_H(in, out1, out2) \
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{ \
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v16i8 tmp_m; \
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\
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tmp_m = __msa_clti_s_b((v16i8) (in), 0); \
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out1 = (v8i16) __msa_ilvr_b(tmp_m, (v16i8) (in)); \
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out2 = (v8i16) __msa_ilvl_b(tmp_m, (v16i8) (in)); \
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}
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|
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#define SWAP_VECS(Vec0, Vec1) \
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{ \
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Vec0 = Vec0 ^ Vec1; \
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Vec1 = Vec0 ^ Vec1; \
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Vec0 = Vec0 ^ Vec1; \
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}
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|
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#endif /* AVUTIL_MIPS_GENERIC_MACROS_MSA_H */
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