ffmpeg

Commit Graph

Author	SHA1	Message	Date
Rémi Denis-Courmont	c1bb19e263	lavu/fixeddsp: RISC-V V butterflies_fixed	2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont	a6c10d05fe	lavu/floatdsp: RISC-V V vector_fmul_scalar This is based on existing code from the VLC git tree with two minor changes to account for the different function prototypes.	2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont	b95e2fbd85	lavu/cpu: detect RISC-V base extensions This introduces compile-time and run-time CPU detection on RISC-V. In practice, I doubt that FFmpeg will ever see a RISC-V CPU without all of I, F and D extensions, and if it does, it probably won't have run-time detection. So the flags are essentially always set. But as things stand, checkasm wants them that way. Compare the ARMV8 flag on AArch64. We are nowhere near running short on CPU flag bits.	2022-09-27 13:19:52 +02:00

Author

SHA1

Message

Date

Rémi Denis-Courmont

c1bb19e263

lavu/fixeddsp: RISC-V V butterflies_fixed

2022-09-27 13:19:52 +02:00

Rémi Denis-Courmont

a6c10d05fe

lavu/floatdsp: RISC-V V vector_fmul_scalar

This is based on existing code from the VLC git tree with two minor
changes to account for the different function prototypes.

2022-09-27 13:19:52 +02:00

Rémi Denis-Courmont

b95e2fbd85

lavu/cpu: detect RISC-V base extensions

This introduces compile-time and run-time CPU detection on RISC-V. In
practice, I doubt that FFmpeg will ever see a RISC-V CPU without all of
I, F and D extensions, and if it does, it probably won't have run-time
detection. So the flags are essentially always set.

But as things stand, checkasm wants them that way. Compare the ARMV8
flag on AArch64. We are nowhere near running short on CPU flag bits.

2022-09-27 13:19:52 +02:00

3 Commits