7 Commits

Author	SHA1	Message	Date
Rémi Denis-Courmont	e50f8e861b	swscale/rgb2rgb: avoid S-regs in RISC-V V uyvytoyuv422 ... We can make do with callee-clobbered registers only now. As an added bonus, this makes the code XLEN-independent.	2023-10-03 20:48:39 +03:00
Rémi Denis-Courmont	1a4bd76ea5	swscale/rgb2rgb: remove R-V V shuffle_bytes_3012 ... This is slower than the Zbb version on real hardware due to register strides. Proper support for vector byte-swap requires the Zvbb extension, but it's much too early for me to worry about it.	2023-10-02 22:28:38 +03:00
Rémi Denis-Courmont	c4a144c29d	swscale/rgb2rgb: add R-V Zbb shuffle_bytes_3210	2023-10-02 22:28:25 +03:00
Rémi Denis-Courmont	b6585eb04c	lavu: add/use flag for RISC-V Zba extension ... The code was blindly assuming that Zbb or V implied Zba. While the earlier is practically always true, the later broke some QEMU setups, as V was introduced earlier than Zba.	2023-07-19 19:29:35 +03:00
Rémi Denis-Courmont	a1bfb5290e	sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 ... This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.	2022-09-30 07:25:44 +02:00
Rémi Denis-Courmont	9181835a24	sws/rgb2rgb: RISC-V V interleaveBytes	2022-09-30 07:24:09 +02:00
Rémi Denis-Courmont	66a03f4053	sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions	2022-09-30 07:24:09 +02:00