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lavc/aacpsdsp: unroll RISC-V V hybrid_synthesis_deint
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@ -203,12 +203,12 @@ func ff_ps_hybrid_synthesis_deint_rvv, zve32x
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mv t4, a4
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mv t4, a4
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addi a2, a2, 1
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addi a2, a2, 1
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2:
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2:
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vsetvli t5, t3, e32, m1, ta, ma
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vsetvli t5, t3, e32, m4, ta, ma
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vlseg2e32.v v16, (t1)
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vlseg2e32.v v16, (t1)
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sub t3, t3, t5
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sub t3, t3, t5
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vsse32.v v16, (t0), t6
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vsse32.v v16, (t0), t6
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mul t2, t5, t6
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mul t2, t5, t6
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vsse32.v v17, (t4), t6
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vsse32.v v20, (t4), t6
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sh3add t1, t5, t1
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sh3add t1, t5, t1
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add t0, t0, t2
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add t0, t0, t2
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add t4, t4, t2
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add t4, t4, t2
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