mirror of https://git.ffmpeg.org/ffmpeg.git
x86: hpeldsp: implement SSE2 versions
Those are mostly used in codecs older than H.264, eg MPEG-2.
put16 versions:
mmx mmx2 sse2
x2: 1888 1185 552
y2: 1778 1092 510
avg16 xy2: 3509(mmx2) -> 2169(sse2)
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Christophe Gisquet
Michael Niedermayer
parent
9eaa8c22bc
commit
f0aca50e0b
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@ -35,21 +35,39 @@ SECTION_TEXT
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; void ff_put_pixels8_x2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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%macro PUT_PIXELS8_X2 0
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%if cpuflag(sse2)
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cglobal put_pixels16_x2, 4,5,4
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%else
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cglobal put_pixels8_x2, 4,5
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%endif
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lea r4, [r2*2]
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.loop:
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mova m0, [r1]
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mova m1, [r1+r2]
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PAVGB m0, [r1+1]
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PAVGB m1, [r1+r2+1]
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movu m0, [r1+1]
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movu m1, [r1+r2+1]
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%if cpuflag(sse2)
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movu m2, [r1]
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movu m3, [r1+r2]
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pavgb m0, m2
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pavgb m1, m3
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%else
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PAVGB m0, [r1]
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PAVGB m1, [r1+r2]
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%endif
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mova [r0], m0
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mova [r0+r2], m1
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add r1, r4
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add r0, r4
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mova m0, [r1]
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mova m1, [r1+r2]
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PAVGB m0, [r1+1]
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PAVGB m1, [r1+r2+1]
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movu m0, [r1+1]
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movu m1, [r1+r2+1]
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%if cpuflag(sse2)
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movu m2, [r1]
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movu m3, [r1+r2]
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pavgb m0, m2
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pavgb m1, m3
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%else
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PAVGB m0, [r1]
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PAVGB m1, [r1+r2]
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%endif
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add r1, r4
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mova [r0], m0
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mova [r0+r2], m1
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@ -107,6 +125,9 @@ INIT_MMX mmxext
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PUT_PIXELS_16
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INIT_MMX 3dnow
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PUT_PIXELS_16
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; The 8_X2 macro can easily be used here
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INIT_XMM sse2
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PUT_PIXELS8_X2
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; void ff_put_no_rnd_pixels8_x2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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@ -199,20 +220,24 @@ PUT_NO_RND_PIXELS8_X2_EXACT
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; void ff_put_pixels8_y2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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%macro PUT_PIXELS8_Y2 0
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%if cpuflag(sse2)
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cglobal put_pixels16_y2, 4,5,3
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%else
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cglobal put_pixels8_y2, 4,5
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%endif
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lea r4, [r2*2]
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mova m0, [r1]
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movu m0, [r1]
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sub r0, r2
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.loop:
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mova m1, [r1+r2]
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mova m2, [r1+r4]
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movu m1, [r1+r2]
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movu m2, [r1+r4]
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add r1, r4
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PAVGB m0, m1
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PAVGB m1, m2
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mova [r0+r2], m0
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mova [r0+r4], m1
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mova m1, [r1+r2]
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mova m0, [r1+r4]
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movu m1, [r1+r2]
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movu m0, [r1+r4]
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add r0, r4
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add r1, r4
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PAVGB m2, m1
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@ -229,6 +254,9 @@ INIT_MMX mmxext
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PUT_PIXELS8_Y2
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INIT_MMX 3dnow
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PUT_PIXELS8_Y2
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; actually, put_pixels16_y2_sse2
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INIT_XMM sse2
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PUT_PIXELS8_Y2
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; void ff_put_no_rnd_pixels8_y2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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@ -352,34 +380,50 @@ AVG_PIXELS8
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%endmacro
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%macro AVG_PIXELS8_X2 0
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%if cpuflag(sse2)
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cglobal avg_pixels16_x2, 4,5,4
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%else
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cglobal avg_pixels8_x2, 4,5
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%endif
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lea r4, [r2*2]
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%if notcpuflag(mmxext)
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pcmpeqd m5, m5
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paddb m5, m5
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%endif
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.loop:
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mova m0, [r1]
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mova m2, [r1+r2]
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movu m0, [r1]
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movu m2, [r1+r2]
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%if notcpuflag(mmxext)
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PAVGB_MMX [r1+1], m0, m3, m5
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PAVGB_MMX [r1+r2+1], m2, m4, m5
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PAVGB_MMX [r0], m0, m3, m5
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PAVGB_MMX [r0+r2], m2, m4, m5
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%else
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%if cpuflag(sse2)
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movu m1, [r1+1]
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movu m3, [r1+r2+1]
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pavgb m0, m1
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pavgb m2, m3
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%else
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PAVGB m0, [r1+1]
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PAVGB m2, [r1+r2+1]
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%endif
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PAVGB m0, [r0]
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PAVGB m2, [r0+r2]
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%endif
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add r1, r4
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mova [r0], m0
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mova [r0+r2], m2
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mova m0, [r1]
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mova m2, [r1+r2]
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movu m0, [r1]
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movu m2, [r1+r2]
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%if notcpuflag(mmxext)
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PAVGB_MMX [r1+1], m0, m3, m5
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PAVGB_MMX [r1+r2+1], m2, m4, m5
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%elif cpuflag(sse2)
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movu m1, [r1+1]
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movu m3, [r1+r2+1]
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pavgb m0, m1
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pavgb m2, m3
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%else
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PAVGB m0, [r1+1]
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PAVGB m2, [r1+r2+1]
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@ -389,6 +433,9 @@ cglobal avg_pixels8_x2, 4,5
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%if notcpuflag(mmxext)
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PAVGB_MMX [r0], m0, m3, m5
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PAVGB_MMX [r0+r2], m2, m4, m5
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%elif cpuflag(sse2)
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pavgb m0, [r0]
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pavgb m2, [r0+r2]
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%else
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PAVGB m0, [r0]
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PAVGB m2, [r0+r2]
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@ -407,36 +454,39 @@ INIT_MMX mmxext
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AVG_PIXELS8_X2
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INIT_MMX 3dnow
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AVG_PIXELS8_X2
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; actually avg_pixels16_x2
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INIT_XMM sse2
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AVG_PIXELS8_X2
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; void ff_avg_pixels8_y2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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%macro AVG_PIXELS8_Y2 0
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%if cpuflag(sse2)
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cglobal avg_pixels16_y2, 4,5,3
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%else
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cglobal avg_pixels8_y2, 4,5
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%endif
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lea r4, [r2*2]
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mova m0, [r1]
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movu m0, [r1]
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sub r0, r2
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.loop:
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mova m1, [r1+r2]
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mova m2, [r1+r4]
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movu m1, [r1+r2]
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movu m2, [r1+r4]
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add r1, r4
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PAVGB m0, m1
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PAVGB m1, m2
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mova m3, [r0+r2]
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mova m4, [r0+r4]
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PAVGB m0, m3
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PAVGB m1, m4
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PAVGB m0, [r0+r2]
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PAVGB m1, [r0+r4]
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mova [r0+r2], m0
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mova [r0+r4], m1
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mova m1, [r1+r2]
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mova m0, [r1+r4]
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movu m1, [r1+r2]
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movu m0, [r1+r4]
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PAVGB m2, m1
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PAVGB m1, m0
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add r0, r4
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add r1, r4
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mova m3, [r0+r2]
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mova m4, [r0+r4]
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PAVGB m2, m3
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PAVGB m1, m4
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PAVGB m2, [r0+r2]
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PAVGB m1, [r0+r4]
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mova [r0+r2], m2
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mova [r0+r4], m1
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add r0, r4
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@ -449,6 +499,9 @@ INIT_MMX mmxext
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AVG_PIXELS8_Y2
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INIT_MMX 3dnow
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AVG_PIXELS8_Y2
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; actually avg_pixels16_y2
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INIT_XMM sse2
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AVG_PIXELS8_Y2
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; void ff_avg_pixels8_xy2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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@ -571,3 +624,5 @@ INIT_MMX mmxext
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AVG_PIXELS_XY2
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INIT_MMX 3dnow
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AVG_PIXELS_XY2
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INIT_XMM sse2
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AVG_PIXELS_XY2
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@ -40,6 +40,16 @@ void ff_put_pixels16_x2_mmxext(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_put_pixels16_x2_3dnow(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_put_pixels16_x2_sse2(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_avg_pixels16_x2_sse2(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_put_pixels16_y2_sse2(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_avg_pixels16_y2_sse2(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_avg_pixels16_xy2_sse2(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_put_no_rnd_pixels8_x2_mmxext(uint8_t *block, const uint8_t *pixels,
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ptrdiff_t line_size, int h);
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void ff_put_no_rnd_pixels8_x2_3dnow(uint8_t *block, const uint8_t *pixels,
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@ -284,7 +294,12 @@ static void hpeldsp_init_sse2(HpelDSPContext *c, int flags, int cpu_flags)
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// these functions are slower than mmx on AMD, but faster on Intel
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c->put_pixels_tab[0][0] = ff_put_pixels16_sse2;
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c->put_no_rnd_pixels_tab[0][0] = ff_put_pixels16_sse2;
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c->put_pixels_tab[0][1] = ff_put_pixels16_x2_sse2;
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c->put_pixels_tab[0][2] = ff_put_pixels16_y2_sse2;
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c->avg_pixels_tab[0][0] = ff_avg_pixels16_sse2;
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c->avg_pixels_tab[0][1] = ff_avg_pixels16_x2_sse2;
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c->avg_pixels_tab[0][2] = ff_avg_pixels16_y2_sse2;
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c->avg_pixels_tab[0][3] = ff_avg_pixels16_xy2_sse2;
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}
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#endif /* HAVE_SSE2_EXTERNAL */
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}
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