mirror of https://git.ffmpeg.org/ffmpeg.git
x86 cpu capabilities detection rewrite / cleanup
Originally committed as revision 3750 to svn://svn.ffmpeg.org/ffmpeg/trunk
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@ -1169,6 +1169,7 @@ typedef struct AVCodecContext {
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#define FF_MM_MMXEXT 0x0002 /* SSE integer functions or AMD MMX ext */
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#define FF_MM_MMXEXT 0x0002 /* SSE integer functions or AMD MMX ext */
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#define FF_MM_SSE 0x0008 /* SSE functions */
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#define FF_MM_SSE 0x0008 /* SSE functions */
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#define FF_MM_SSE2 0x0010 /* PIV SSE2 functions */
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#define FF_MM_SSE2 0x0010 /* PIV SSE2 functions */
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#define FF_MM_3DNOWEXT 0x0020 /* AMD 3DNowExt */
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#endif /* HAVE_MMX */
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#endif /* HAVE_MMX */
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/**
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/**
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@ -408,6 +408,7 @@ int mm_support(void);
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#define MM_MMXEXT 0x0002 /* SSE integer functions or AMD MMX ext */
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#define MM_MMXEXT 0x0002 /* SSE integer functions or AMD MMX ext */
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#define MM_SSE 0x0008 /* SSE functions */
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#define MM_SSE 0x0008 /* SSE functions */
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#define MM_SSE2 0x0010 /* PIV SSE2 functions */
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#define MM_SSE2 0x0010 /* PIV SSE2 functions */
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#define MM_3DNOWEXT 0x0020 /* AMD 3DNowExt */
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extern int mm_flags;
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extern int mm_flags;
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@ -27,6 +27,7 @@ int mm_support(void)
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{
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{
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int rval = 0;
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int rval = 0;
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int eax, ebx, ecx, edx;
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int eax, ebx, ecx, edx;
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int max_std_level, max_ext_level, std_caps=0, ext_caps=0;
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long a, c;
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long a, c;
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__asm__ __volatile__ (
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__asm__ __volatile__ (
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@ -52,58 +53,44 @@ int mm_support(void)
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if (a == c)
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if (a == c)
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return 0; /* CPUID not supported */
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return 0; /* CPUID not supported */
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cpuid(0, eax, ebx, ecx, edx);
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if (ebx == 0x756e6547 &&
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cpuid(0, max_std_level, ebx, ecx, edx);
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edx == 0x49656e69 &&
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ecx == 0x6c65746e) {
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if(max_std_level >= 1){
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cpuid(1, eax, ebx, ecx, std_caps);
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/* intel */
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if (std_caps & (1<<23))
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inteltest:
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rval |= MM_MMX;
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cpuid(1, eax, ebx, ecx, edx);
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if (std_caps & (1<<25))
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if ((edx & 0x00800000) == 0)
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return 0;
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rval |= MM_MMX;
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if (edx & 0x02000000)
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rval |= MM_MMXEXT | MM_SSE;
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rval |= MM_MMXEXT | MM_SSE;
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if (edx & 0x04000000)
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if (std_caps & (1<<26))
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rval |= MM_SSE2;
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rval |= MM_SSE2;
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return rval;
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}
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} else if (ebx == 0x68747541 &&
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cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
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if(max_ext_level >= 0x80000001){
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cpuid(0x80000001, eax, ebx, ecx, ext_caps);
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if (ext_caps & (1<<31))
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rval |= MM_3DNOW;
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if (ext_caps & (1<<30))
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rval |= MM_3DNOWEXT;
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if (ext_caps & (1<<23))
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rval |= MM_MMX;
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}
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cpuid(0, eax, ebx, ecx, edx);
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if ( ebx == 0x68747541 &&
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edx == 0x69746e65 &&
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edx == 0x69746e65 &&
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ecx == 0x444d4163) {
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ecx == 0x444d4163) {
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/* AMD */
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/* AMD */
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cpuid(0x80000000, eax, ebx, ecx, edx);
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if(ext_caps & (1<<22))
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if ((unsigned)eax < 0x80000001)
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goto inteltest;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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if ((edx & 0x00800000) == 0)
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return 0;
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rval = MM_MMX;
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if (edx & 0x80000000)
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rval |= MM_3DNOW;
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if (edx & 0x00400000)
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rval |= MM_MMXEXT;
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rval |= MM_MMXEXT;
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goto inteltest;
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} else if (ebx == 0x746e6543 &&
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} else if (ebx == 0x746e6543 &&
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edx == 0x48727561 &&
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edx == 0x48727561 &&
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ecx == 0x736c7561) { /* "CentaurHauls" */
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ecx == 0x736c7561) { /* "CentaurHauls" */
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/* VIA C3 */
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/* VIA C3 */
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cpuid(0x80000000, eax, ebx, ecx, edx);
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if(ext_caps & (1<<24))
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if ((unsigned)eax < 0x80000001)
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goto inteltest;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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rval = 0;
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if( edx & ( 1 << 31) )
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rval |= MM_3DNOW;
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if( edx & ( 1 << 23) )
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rval |= MM_MMX;
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if( edx & ( 1 << 24) )
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rval |= MM_MMXEXT;
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rval |= MM_MMXEXT;
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if(rval==0)
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goto inteltest;
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return rval;
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} else if (ebx == 0x69727943 &&
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} else if (ebx == 0x69727943 &&
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edx == 0x736e4978 &&
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edx == 0x736e4978 &&
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ecx == 0x64616574) {
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ecx == 0x64616574) {
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@ -116,29 +103,21 @@ int mm_support(void)
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According to the table, the only CPU which supports level
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According to the table, the only CPU which supports level
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2 is also the only one which supports extended CPUID levels.
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2 is also the only one which supports extended CPUID levels.
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*/
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*/
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if (eax != 2)
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if (eax < 2)
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goto inteltest;
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return rval;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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if (ext_caps & (1<<24))
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if ((eax & 0x00800000) == 0)
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return 0;
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rval = MM_MMX;
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if (eax & 0x01000000)
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rval |= MM_MMXEXT;
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rval |= MM_MMXEXT;
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return rval;
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} else if (ebx == 0x756e6547 &&
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edx == 0x54656e69 &&
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ecx == 0x3638784d) {
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/* Tranmeta Crusoe */
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cpuid(0x80000000, eax, ebx, ecx, edx);
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if ((unsigned)eax < 0x80000001)
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return 0;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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if ((edx & 0x00800000) == 0)
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return 0;
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return MM_MMX;
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} else {
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return 0;
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}
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}
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#if 0
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av_log(NULL, AV_LOG_DEBUG, "%s%s%s%s%s%s\n",
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(rval&MM_MMX) ? "MMX ":"",
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(rval&MM_MMXEXT) ? "MMX2 ":"",
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(rval&MM_SSE) ? "SSE ":"",
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(rval&MM_SSE2) ? "SSE2 ":"",
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(rval&MM_3DNOW) ? "3DNow ":"",
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(rval&MM_3DNOWEXT) ? "3DNowExt ":"");
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#endif
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return rval;
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}
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}
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#ifdef __TEST__
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#ifdef __TEST__
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