From f399e406af0c8507bb3ab7b94995ad7b8f409093 Mon Sep 17 00:00:00 2001 From: Kostya Shishkov Date: Wed, 14 Aug 2013 15:28:05 -0400 Subject: [PATCH] altivec: perform an explicit unaligned load MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implicit vector loads on POWER7 hardware can use the VSX instruction set instead of classic Altivec/VMX. Let's force a VMX load in this case. Signed-off-by: Martin Storsjö --- libavcodec/ppc/int_altivec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/libavcodec/ppc/int_altivec.c b/libavcodec/ppc/int_altivec.c index 8357ca768b..38ec99b8c5 100644 --- a/libavcodec/ppc/int_altivec.c +++ b/libavcodec/ppc/int_altivec.c @@ -84,14 +84,12 @@ static int32_t scalarproduct_int16_altivec(const int16_t *v1, const int16_t *v2, { int i; LOAD_ZERO; - const vec_s16 *pv; register vec_s16 vec1; register vec_s32 res = vec_splat_s32(0), t; int32_t ires; for(i = 0; i < order; i += 8){ - pv = (const vec_s16*)v1; - vec1 = vec_perm(pv[0], pv[1], vec_lvsl(0, v1)); + vec1 = vec_unaligned_load(v1); t = vec_msum(vec1, vec_ld(0, v2), zero_s32v); res = vec_sums(t, res); v1 += 8;