From d1326b63479f839bc776c1c250793b9d487818cd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= <remi@remlab.net>
Date: Sat, 27 Jul 2024 15:31:55 +0300
Subject: [PATCH] lavu/riscv: drop probing for zba CPU capability

---
 libavutil/cpu.c           |  1 -
 libavutil/riscv/cpu.c     | 10 +---------
 libavutil/tests/cpu.c     |  1 -
 tests/checkasm/checkasm.c |  1 -
 4 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 6c26182b78..41cee7fa77 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -189,7 +189,6 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
         { "zve32f",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32  },    .unit = "flags" },
         { "zve64x",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64  },    .unit = "flags" },
         { "zve64d",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64  },    .unit = "flags" },
-        { "zba",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_ADDR },    .unit = "flags" },
         { "zbb",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC },   .unit = "flags" },
         { "zvbb",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVBB },   .unit = "flags" },
         { "misaligned", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_MISALIGNED },   .unit = "flags" },
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index 6537e91965..52ca2ce814 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -63,10 +63,6 @@ int ff_get_cpu_flags_riscv(void)
             ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
                  | AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64;
 #endif
-#ifdef RISCV_HWPROBE_EXT_ZBA
-        if (pairs[1].value & RISCV_HWPROBE_EXT_ZBA)
-            ret |= AV_CPU_FLAG_RVB_ADDR;
-#endif
 #ifdef RISCV_HWPROBE_EXT_ZBB
         if (pairs[1].value & RISCV_HWPROBE_EXT_ZBB)
             ret |= AV_CPU_FLAG_RVB_BASIC;
@@ -95,8 +91,7 @@ int ff_get_cpu_flags_riscv(void)
         if (hwcap & HWCAP_RV('I'))
             ret |= AV_CPU_FLAG_RVI;
         if (hwcap & HWCAP_RV('B'))
-            ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC |
-                   AV_CPU_FLAG_RVB;
+            ret |= AV_CPU_FLAG_RVB_BASIC | AV_CPU_FLAG_RVB;
 
         /* The V extension implies all Zve* functional subsets */
         if (hwcap & HWCAP_RV('V'))
@@ -109,9 +104,6 @@ int ff_get_cpu_flags_riscv(void)
     ret |= AV_CPU_FLAG_RVI;
 #endif
 
-#ifdef __riscv_zba
-    ret |= AV_CPU_FLAG_RVB_ADDR;
-#endif
 #ifdef __riscv_zbb
     ret |= AV_CPU_FLAG_RVB_BASIC;
 #endif
diff --git a/libavutil/tests/cpu.c b/libavutil/tests/cpu.c
index e03fbf94eb..0a459c1d9e 100644
--- a/libavutil/tests/cpu.c
+++ b/libavutil/tests/cpu.c
@@ -86,7 +86,6 @@ static const struct {
     { AV_CPU_FLAG_LASX,      "lasx"       },
 #elif ARCH_RISCV
     { AV_CPU_FLAG_RVI,       "rvi"        },
-    { AV_CPU_FLAG_RVB_ADDR,  "zba"        },
     { AV_CPU_FLAG_RVB_BASIC, "zbb"        },
     { AV_CPU_FLAG_RVB,       "rvb"        },
     { AV_CPU_FLAG_RVV_I32,   "zve32x"     },
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index 49b47f8615..58597d3888 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -291,7 +291,6 @@ static const struct {
 #elif ARCH_RISCV
     { "RVI",      "rvi",      AV_CPU_FLAG_RVI },
     { "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED },
-    { "RVBaddr",  "rvb_a",    AV_CPU_FLAG_RVB_ADDR },
     { "RVBbasic", "rvb_b",    AV_CPU_FLAG_RVB_BASIC },
     { "RVB",      "rvb",      AV_CPU_FLAG_RVB },
     { "RVVi32",   "rvv_i32",  AV_CPU_FLAG_RVV_I32 },