lavu/floatdsp: RISC-V V vector_dmac_scalar

This commit is contained in:
Rémi Denis-Courmont 2022-09-26 17:52:33 +03:00 committed by Lynne
parent c3db27ba95
commit d120ab5b91
2 changed files with 21 additions and 0 deletions

View File

@ -34,6 +34,8 @@ void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
int len);
void ff_vector_dmac_scalar_rvv(double *dst, const double *src, double mul,
int len);
void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
int len);
@ -50,6 +52,7 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
if (flags & AV_CPU_FLAG_RVV_F64) {
fdsp->vector_dmul = ff_vector_dmul_rvv;
fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
}
#endif

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@ -91,6 +91,24 @@ func ff_vector_dmul_rvv, zve64d
ret
endfunc
// (a0) += (a1) * fa0 [0..a2-1]
func ff_vector_dmac_scalar_rvv, zve64d
NOHWD fmv.d.x fa0, a2
NOHWD mv a2, a3
1:
vsetvli t0, a2, e64, m1, ta, ma
vle64.v v24, (a1)
sub a2, a2, t0
vle64.v v16, (a0)
sh3add a1, t0, a1
vfmacc.vf v16, fa0, v24
vse64.v v16, (a0)
sh3add a0, t0, a0
bnez a2, 1b
ret
endfunc
// (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_dmul_scalar_rvv, zve64d
NOHWD fmv.d.x fa0, a2