mirror of https://git.ffmpeg.org/ffmpeg.git
avcodec/mips: Improve vp9 idct msa functions
Removed memset calls. Signed-off-by: Kaustubh Raste <kaustubh.raste@imgtec.com> Reviewed-by: Manojkumar Bhosale <Manojkumar.Bhosale@imgtec.com> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
This commit is contained in:
Kaustubh Raste
Michael Niedermayer
parent
2e79813a8e
commit
c75b23cbea
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015 Shivraj Patil (Shivraj.Patil@imgtec.com)
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* Copyright (c) 2015 - 2017 Shivraj Patil (Shivraj.Patil@imgtec.com)
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*
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* This file is part of FFmpeg.
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*
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@ -352,6 +352,7 @@ static void vp9_idct4x4_1_add_msa(int16_t *input, uint8_t *dst,
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out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
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out = ROUND_POWER_OF_TWO(out, 4);
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vec = __msa_fill_h(out);
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input[0] = 0;
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ADDBLK_ST4x4_UB(vec, vec, vec, vec, dst, dst_stride);
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}
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@ -360,9 +361,11 @@ static void vp9_idct4x4_colcol_addblk_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride)
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{
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v8i16 in0, in1, in2, in3;
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v8i16 zero = { 0 };
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/* load vector elements of 4x4 block */
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LD4x4_SH(input, in0, in1, in2, in3);
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ST_SH2(zero, zero, input, 8);
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/* rows */
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VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3);
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/* columns */
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@ -377,9 +380,11 @@ static void vp9_iadst4x4_colcol_addblk_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride)
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{
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v8i16 in0, in1, in2, in3;
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v8i16 zero = { 0 };
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/* load vector elements of 4x4 block */
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LD4x4_SH(input, in0, in1, in2, in3);
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ST_SH2(zero, zero, input, 8);
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/* rows */
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VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3);
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/* columns */
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@ -394,9 +399,11 @@ static void vp9_iadst_idct_4x4_add_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride, int32_t eob)
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{
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v8i16 in0, in1, in2, in3;
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v8i16 zero = { 0 };
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/* load vector elements of 4x4 block */
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LD4x4_SH(input, in0, in1, in2, in3);
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ST_SH2(zero, zero, input, 8);
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/* cols */
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VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3);
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/* columns */
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@ -411,9 +418,11 @@ static void vp9_idct_iadst_4x4_add_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride, int32_t eob)
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{
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v8i16 in0, in1, in2, in3;
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v8i16 zero = { 0 };
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/* load vector elements of 4x4 block */
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LD4x4_SH(input, in0, in1, in2, in3);
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ST_SH2(zero, zero, input, 8);
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/* cols */
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VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3);
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/* columns */
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@ -585,6 +594,7 @@ static void vp9_idct8x8_1_add_msa(int16_t *input, uint8_t *dst,
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out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
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val = ROUND_POWER_OF_TWO(out, 5);
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vec = __msa_fill_h(val);
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input[0] = 0;
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VP9_ADDBLK_ST8x4_UB(dst, dst_stride, vec, vec, vec, vec);
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dst += (4 * dst_stride);
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@ -601,9 +611,9 @@ static void vp9_idct8x8_12_colcol_addblk_msa(int16_t *input, uint8_t *dst,
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/* load vector elements of 8x8 block */
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LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 8);
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ILVR_D2_SH(in1, in0, in3, in2, in0, in1);
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ILVR_D2_SH(in5, in4, in7, in6, in2, in3);
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//TRANSPOSE8X4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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/* stage1 */
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ILVL_H2_SH(in3, in0, in2, in1, s0, s1);
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@ -659,9 +669,11 @@ static void vp9_idct8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride)
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{
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v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
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v8i16 zero = { 0 };
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/* load vector elements of 8x8 block */
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LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 8);
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/* 1D idct8x8 */
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VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
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in0, in1, in2, in3, in4, in5, in6, in7);
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@ -689,10 +701,11 @@ static void vp9_iadst8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst,
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v8i16 out0, out1, out2, out3, out4, out5, out6, out7;
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v8i16 cnst0, cnst1, cnst2, cnst3, cnst4;
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v8i16 temp0, temp1, temp2, temp3, s0, s1;
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v16i8 zero = { 0 };
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v8i16 zero = { 0 };
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/* load vector elements of 8x8 block */
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LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 8);
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/* 1D adst8x8 */
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VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7,
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@ -736,13 +749,13 @@ static void vp9_iadst8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst,
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dst0 = LD_UB(dst + 0 * dst_stride);
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dst7 = LD_UB(dst + 7 * dst_stride);
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res0 = (v8i16) __msa_ilvr_b(zero, (v16i8) dst0);
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res0 = (v8i16) __msa_ilvr_b((v16i8) zero, (v16i8) dst0);
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res0 += out0;
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res0 = CLIP_SH_0_255(res0);
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res0 = (v8i16) __msa_pckev_b((v16i8) res0, (v16i8) res0);
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ST8x1_UB(res0, dst);
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res7 = (v8i16) __msa_ilvr_b(zero, (v16i8) dst7);
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res7 = (v8i16) __msa_ilvr_b((v16i8) zero, (v16i8) dst7);
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res7 += out7;
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res7 = CLIP_SH_0_255(res7);
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res7 = (v8i16) __msa_pckev_b((v16i8) res7, (v16i8) res7);
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@ -809,9 +822,11 @@ static void vp9_iadst_idct_8x8_add_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride, int32_t eob)
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{
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v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
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v8i16 zero = { 0 };
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/* load vector elements of 8x8 block */
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LD_SH8(input, 8, in1, in6, in3, in4, in5, in2, in7, in0);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 8);
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/* 1D idct8x8 */
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VP9_IADST8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
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in0, in1, in2, in3, in4, in5, in6, in7);
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@ -834,9 +849,11 @@ static void vp9_idct_iadst_8x8_add_msa(int16_t *input, uint8_t *dst,
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int32_t dst_stride, int32_t eob)
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{
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v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
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v8i16 zero = { 0 };
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/* load vector elements of 8x8 block */
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LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 8);
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/* 1D idct8x8 */
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VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
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@ -937,12 +954,16 @@ static void vp9_idct16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
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v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14;
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v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15;
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v8i16 tmp5, tmp6, tmp7;
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v8i16 zero = { 0 };
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/* load up 8x8 */
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LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
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/* load up 8x16 */
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LD_SH16(input, 16,
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reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
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reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 16);
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input += 8 * 16;
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/* load bottom 8x8 */
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LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 16);
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VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14);
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VP9_DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6);
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@ -1036,12 +1057,16 @@ static void vp9_idct16_1d_columns_msa(int16_t *input, int16_t *output)
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v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14;
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v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15;
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v8i16 tmp5, tmp6, tmp7;
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v8i16 zero = { 0 };
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/* load up 8x8 */
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LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
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input += 8 * 16;
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/* load bottom 8x8 */
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LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
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/* load up 8x16 */
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LD_SH16(input, 16,
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reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
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reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 16);
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input += 16 * 8;
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 16);
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VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14);
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VP9_DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6);
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@ -1141,11 +1166,11 @@ static void vp9_idct16x16_1_add_msa(int16_t *input, uint8_t *dst,
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out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), VP9_DCT_CONST_BITS);
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out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
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out = ROUND_POWER_OF_TWO(out, 6);
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input[0] = 0;
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vec = __msa_fill_h(out);
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for (i = 4; i--;)
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{
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for (i = 4; i--;) {
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LD_UB4(dst, dst_stride, dst0, dst1, dst2, dst3);
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UNPCK_UB_SH(dst0, res0, res4);
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UNPCK_UB_SH(dst1, res1, res5);
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@ -1229,12 +1254,17 @@ static void vp9_iadst16_1d_columns_msa(int16_t *input, int16_t *output)
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{
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v8i16 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
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v8i16 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15;
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v8i16 zero = { 0 };
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/* load input data */
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LD_SH16(input, 16,
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l0, l1, l2, l3, l4, l5, l6, l7,
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l8, l9, l10, l11, l12, l13, l14, l15);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 16);
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input += 16 * 8;
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, input, 16);
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/* ADST in horizontal */
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VP9_IADST8x16_1D(l0, l1, l2, l3, l4, l5, l6, l7,
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l8, l9, l10, l11, l12, l13, l14, l15,
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@ -1591,9 +1621,11 @@ static void vp9_idct8x32_column_even_process_store(int16_t *tmp_buf,
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v8i16 vec0, vec1, vec2, vec3, loc0, loc1, loc2, loc3;
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v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
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v8i16 stp0, stp1, stp2, stp3, stp4, stp5, stp6, stp7;
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v8i16 zero = { 0 };
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/* Even stage 1 */
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LD_SH8(tmp_buf, (4 * 32), reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, tmp_buf, (4 * 32));
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tmp_buf += (2 * 32);
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VP9_DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7);
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@ -1613,6 +1645,7 @@ static void vp9_idct8x32_column_even_process_store(int16_t *tmp_buf,
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/* Even stage 2 */
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/* Load 8 */
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LD_SH8(tmp_buf, (4 * 32), reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
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ST_SH8(zero, zero, zero, zero, zero, zero, zero, zero, tmp_buf, (4 * 32));
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VP9_DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7);
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VP9_DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3);
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@ -1671,6 +1704,7 @@ static void vp9_idct8x32_column_odd_process_store(int16_t *tmp_buf,
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{
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v8i16 vec0, vec1, vec2, vec3, loc0, loc1, loc2, loc3;
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v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
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v8i16 zero = { 0 };
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/* Odd stage 1 */
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reg0 = LD_SH(tmp_buf + 32);
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@ -1682,6 +1716,15 @@ static void vp9_idct8x32_column_odd_process_store(int16_t *tmp_buf,
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reg6 = LD_SH(tmp_buf + 25 * 32);
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reg7 = LD_SH(tmp_buf + 31 * 32);
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ST_SH(zero, tmp_buf + 32);
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ST_SH(zero, tmp_buf + 7 * 32);
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ST_SH(zero, tmp_buf + 9 * 32);
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ST_SH(zero, tmp_buf + 15 * 32);
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ST_SH(zero, tmp_buf + 17 * 32);
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ST_SH(zero, tmp_buf + 23 * 32);
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ST_SH(zero, tmp_buf + 25 * 32);
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ST_SH(zero, tmp_buf + 31 * 32);
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VP9_DOTP_CONST_PAIR(reg0, reg7, cospi_31_64, cospi_1_64, reg0, reg7);
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VP9_DOTP_CONST_PAIR(reg4, reg3, cospi_15_64, cospi_17_64, reg3, reg4);
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VP9_DOTP_CONST_PAIR(reg2, reg5, cospi_23_64, cospi_9_64, reg2, reg5);
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@ -1723,6 +1766,15 @@ static void vp9_idct8x32_column_odd_process_store(int16_t *tmp_buf,
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reg6 = LD_SH(tmp_buf + 27 * 32);
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reg7 = LD_SH(tmp_buf + 29 * 32);
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ST_SH(zero, tmp_buf + 3 * 32);
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ST_SH(zero, tmp_buf + 5 * 32);
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ST_SH(zero, tmp_buf + 11 * 32);
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ST_SH(zero, tmp_buf + 13 * 32);
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ST_SH(zero, tmp_buf + 19 * 32);
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ST_SH(zero, tmp_buf + 21 * 32);
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ST_SH(zero, tmp_buf + 27 * 32);
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ST_SH(zero, tmp_buf + 29 * 32);
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VP9_DOTP_CONST_PAIR(reg1, reg6, cospi_27_64, cospi_5_64, reg1, reg6);
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VP9_DOTP_CONST_PAIR(reg5, reg2, cospi_11_64, cospi_21_64, reg2, reg5);
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VP9_DOTP_CONST_PAIR(reg3, reg4, cospi_19_64, cospi_13_64, reg3, reg4);
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@ -1901,11 +1953,11 @@ static void vp9_idct32x32_1_add_msa(int16_t *input, uint8_t *dst,
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out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), VP9_DCT_CONST_BITS);
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out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
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out = ROUND_POWER_OF_TWO(out, 6);
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input[0] = 0;
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vec = __msa_fill_h(out);
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for (i = 16; i--;)
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{
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for (i = 16; i--;) {
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LD_UB2(dst, 16, dst0, dst1);
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LD_UB2(dst + dst_stride, 16, dst2, dst3);
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@ -2004,11 +2056,9 @@ void ff_idct_idct_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
|
|||
{
|
||||
if (eob > 1) {
|
||||
vp9_idct4x4_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 4 * 4 * sizeof(*block));
|
||||
}
|
||||
else {
|
||||
vp9_idct4x4_1_add_msa(block, dst, stride);
|
||||
block[0] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2017,60 +2067,41 @@ void ff_idct_idct_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
|
|||
{
|
||||
if (eob == 1) {
|
||||
vp9_idct8x8_1_add_msa(block, dst, stride);
|
||||
block[0] = 0;
|
||||
}
|
||||
else if (eob <= 12) {
|
||||
vp9_idct8x8_12_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 4 * 8 * sizeof(*block));
|
||||
}
|
||||
else {
|
||||
vp9_idct8x8_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 8 * 8 * sizeof(*block));
|
||||
}
|
||||
}
|
||||
|
||||
void ff_idct_idct_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (eob == 1) {
|
||||
/* DC only DCT coefficient. */
|
||||
vp9_idct16x16_1_add_msa(block, dst, stride);
|
||||
block[0] = 0;
|
||||
}
|
||||
else if (eob <= 10) {
|
||||
vp9_idct16x16_10_colcol_addblk_msa(block, dst, stride);
|
||||
for (i = 0; i < 4; ++i) {
|
||||
memset(block, 0, 4 * sizeof(*block));
|
||||
block += 16;
|
||||
}
|
||||
}
|
||||
else {
|
||||
vp9_idct16x16_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 16 * 16 * sizeof(*block));
|
||||
}
|
||||
}
|
||||
|
||||
void ff_idct_idct_32x32_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (eob == 1) {
|
||||
vp9_idct32x32_1_add_msa(block, dst, stride);
|
||||
block[0] = 0;
|
||||
}
|
||||
else if (eob <= 34) {
|
||||
vp9_idct32x32_34_colcol_addblk_msa(block, dst, stride);
|
||||
for (i = 0; i < 8; ++i) {
|
||||
memset(block, 0, 8 * sizeof(*block));
|
||||
block += 32;
|
||||
}
|
||||
}
|
||||
else {
|
||||
vp9_idct32x32_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 32 * 32 * sizeof(*block));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2078,61 +2109,52 @@ void ff_iadst_iadst_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
|
|||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_iadst4x4_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 4 * 4 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_iadst_iadst_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_iadst8x8_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 8 * 8 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_iadst_iadst_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_iadst16x16_colcol_addblk_msa(block, dst, stride);
|
||||
memset(block, 0, 16 * 16 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_idct_iadst_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_idct_iadst_4x4_add_msa(block, dst, stride, eob);
|
||||
memset(block, 0, 4 * 4 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_idct_iadst_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_idct_iadst_8x8_add_msa(block, dst, stride, eob);
|
||||
memset(block, 0, 8 * 8 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_idct_iadst_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_idct_iadst_16x16_add_msa(block, dst, stride, eob);
|
||||
memset(block, 0, 16 * 16 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_iadst_idct_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_iadst_idct_4x4_add_msa(block, dst, stride, eob);
|
||||
memset(block, 0, 4 * 4 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_iadst_idct_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_iadst_idct_8x8_add_msa(block, dst, stride, eob);
|
||||
memset(block, 0, 8 * 8 * sizeof(*block));
|
||||
}
|
||||
|
||||
void ff_iadst_idct_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
|
||||
int16_t *block, int eob)
|
||||
{
|
||||
vp9_iadst_idct_16x16_add_msa(block, dst, stride, eob);
|
||||
memset(block, 0, 16 * 16 * sizeof(*block));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue