mirror of https://git.ffmpeg.org/ffmpeg.git
avcodec/x86: cleanup simple_idct10
Use named arguments for the functions so we can remove a define. The stride/linesize argument is now ptrdiff_t type so we no longer need to sign extend the register.
This commit is contained in:
James Darnley
parent
e3db94302c
commit
8781330d80
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@ -51,7 +51,7 @@ cextern w7_min_w5
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SECTION .text
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%macro idct_fn 0
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cglobal prores_idct_put_10, 4, 4, 15
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cglobal prores_idct_put_10, 4, 4, 15, pixels, lsize, block, qmat
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IDCT_FN pw_1, 15, pw_88, 18, pw_4, pw_1019, r3
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RET
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%endmacro
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@ -68,21 +68,21 @@ CONST_DEC w7_min_w5, W7sh2, -W5sh2
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SECTION .text
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%macro idct_fn 0
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cglobal simple_idct10, 1, 1, 16
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cglobal simple_idct10, 1, 1, 16, block
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IDCT_FN "", 12, "", 19
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RET
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cglobal simple_idct10_put, 3, 3, 16
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cglobal simple_idct10_put, 3, 3, 16, pixels, lsize, block
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IDCT_FN "", 12, "", 19, 0, pw_1023
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RET
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cglobal simple_idct12, 1, 1, 16
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cglobal simple_idct12, 1, 1, 16, block
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; coeffs are already 15bits, adding the offset would cause
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; overflow in the input
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IDCT_FN "", 15, pw_2, 16
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RET
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cglobal simple_idct12_put, 3, 3, 16
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cglobal simple_idct12_put, 3, 3, 16, pixels, lsize, block
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; range isn't known, so the C simple_idct range is used
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; Also, using a bias on input overflows, so use the bias
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; on output of the first butterfly instead
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@ -115,18 +115,18 @@
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psubd m3, m9 ; a1[4-7] intermediate
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; load/store
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mova [COEFFS+ 0], m0
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mova [COEFFS+ 32], m2
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mova [COEFFS+ 64], m4
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mova [COEFFS+ 96], m6
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mova m10,[COEFFS+ 16] ; { row[1] }[0-7]
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mova m8, [COEFFS+ 48] ; { row[3] }[0-7]
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mova m13,[COEFFS+ 80] ; { row[5] }[0-7]
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mova m14,[COEFFS+112] ; { row[7] }[0-7]
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mova [COEFFS+ 16], m1
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mova [COEFFS+ 48], m3
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mova [COEFFS+ 80], m5
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mova [COEFFS+112], m7
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mova [blockq+ 0], m0
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mova [blockq+ 32], m2
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mova [blockq+ 64], m4
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mova [blockq+ 96], m6
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mova m10,[blockq+ 16] ; { row[1] }[0-7]
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mova m8, [blockq+ 48] ; { row[3] }[0-7]
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mova m13,[blockq+ 80] ; { row[5] }[0-7]
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mova m14,[blockq+112] ; { row[7] }[0-7]
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mova [blockq+ 16], m1
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mova [blockq+ 48], m3
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mova [blockq+ 80], m5
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mova [blockq+112], m7
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%if %0 == 3
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pmullw m10,[%3+ 16]
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pmullw m8, [%3+ 48]
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@ -197,17 +197,17 @@
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; row[5] = (a2 - b2) >> 15;
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; row[3] = (a3 + b3) >> 15;
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; row[4] = (a3 - b3) >> 15;
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mova m8, [COEFFS+ 0] ; a0[0-3]
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mova m9, [COEFFS+16] ; a0[4-7]
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mova m8, [blockq+ 0] ; a0[0-3]
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mova m9, [blockq+16] ; a0[4-7]
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SUMSUB_SHPK m8, m9, m10, m11, m0, m1, %2
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mova m0, [COEFFS+32] ; a1[0-3]
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mova m1, [COEFFS+48] ; a1[4-7]
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mova m0, [blockq+32] ; a1[0-3]
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mova m1, [blockq+48] ; a1[4-7]
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SUMSUB_SHPK m0, m1, m9, m11, m2, m3, %2
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mova m1, [COEFFS+64] ; a2[0-3]
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mova m2, [COEFFS+80] ; a2[4-7]
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mova m1, [blockq+64] ; a2[0-3]
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mova m2, [blockq+80] ; a2[4-7]
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SUMSUB_SHPK m1, m2, m11, m3, m4, m5, %2
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mova m2, [COEFFS+96] ; a3[0-3]
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mova m3, [COEFFS+112] ; a3[4-7]
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mova m2, [blockq+96] ; a3[0-3]
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mova m3, [blockq+112] ; a3[4-7]
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SUMSUB_SHPK m2, m3, m4, m5, m6, m7, %2
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%endmacro
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@ -223,20 +223,12 @@
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; %7 = qmat (for prores)
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%macro IDCT_FN 4-7
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%if %0 == 4
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; No clamping, means pure idct
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%xdefine COEFFS r0
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%else
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movsxd r1, r1d
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%xdefine COEFFS r2
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%endif
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; for (i = 0; i < 8; i++)
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; idctRowCondDC(block + i*8);
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mova m10,[COEFFS+ 0] ; { row[0] }[0-7]
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mova m8, [COEFFS+32] ; { row[2] }[0-7]
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mova m13,[COEFFS+64] ; { row[4] }[0-7]
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mova m12,[COEFFS+96] ; { row[6] }[0-7]
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mova m10,[blockq+ 0] ; { row[0] }[0-7]
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mova m8, [blockq+32] ; { row[2] }[0-7]
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mova m13,[blockq+64] ; { row[4] }[0-7]
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mova m12,[blockq+96] ; { row[6] }[0-7]
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%if %0 == 7
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pmullw m10,[%7+ 0]
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@ -251,10 +243,10 @@
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; transpose for second part of IDCT
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TRANSPOSE8x8W 8, 0, 1, 2, 4, 11, 9, 10, 3
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mova [COEFFS+ 16], m0
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mova [COEFFS+ 48], m2
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mova [COEFFS+ 80], m11
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mova [COEFFS+112], m10
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mova [blockq+ 16], m0
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mova [blockq+ 48], m2
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mova [blockq+ 80], m11
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mova [blockq+112], m10
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SWAP 8, 10
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SWAP 1, 8
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SWAP 4, 13
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@ -267,14 +259,14 @@
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; clip/store
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%if %0 == 4
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; No clamping, means pure idct
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mova [r0+ 0], m8
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mova [r0+ 16], m0
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mova [r0+ 32], m1
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mova [r0+ 48], m2
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mova [r0+ 64], m4
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mova [r0+ 80], m11
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mova [r0+ 96], m9
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mova [r0+112], m10
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mova [blockq+ 0], m8
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mova [blockq+ 16], m0
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mova [blockq+ 32], m1
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mova [blockq+ 48], m2
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mova [blockq+ 64], m4
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mova [blockq+ 80], m11
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mova [blockq+ 96], m9
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mova [blockq+112], m10
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%else
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%ifidn %5, 0
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pxor m3, m3
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