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lavu/riscv: remove bespoke assembler for MIN
This is no longer necessary as Zbb is now always explicitly required.
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@ -95,11 +95,6 @@
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shnadd 3, \rd, \rs1, \rs2
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shnadd 3, \rd, \rs1, \rs2
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.endm
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.endm
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#endif
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#endif
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#if !defined (__riscv_zbb)
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.macro min rd, rs1, rs2
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.insn r OP, 4, 5, \rd, \rs1, \rs2
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.endm
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#endif
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/* Convenience macro to load a Vector type (vtype) as immediate */
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/* Convenience macro to load a Vector type (vtype) as immediate */
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.macro lvtypei rd, e, m=m1, tp=tu, mp=mu
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.macro lvtypei rd, e, m=m1, tp=tu, mp=mu
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