lavu/riscv: remove bespoke assembler for MIN

This is no longer necessary as Zbb is now always explicitly required.
2024-05-07 21:08:43 +03:00 · 2024-05-07 21:08:43 +03:00 · 5afe734b6d
parent 6c6313f1b5
commit 5afe734b6d
1 changed files with 0 additions and 5 deletions
--- a/libavutil/riscv/asm.S
+++ b/libavutil/riscv/asm.S
@ -95,11 +95,6 @@
        shnadd  3, \rd, \rs1, \rs2
        .endm
 #endif
-#if !defined (__riscv_zbb)
-        .macro  min rd, rs1, rs2
-        .insn r OP, 4, 5, \rd, \rs1, \rs2
-        .endm
-#endif

        /* Convenience macro to load a Vector type (vtype) as immediate */
        .macro  lvtypei rd, e, m=m1, tp=tu, mp=mu