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lavc/vp9dsp: R-V V mc bilin hv 

C908   X60
vp9_avg_bilin_4hv_8bpp_c                           :   10.7    9.5
vp9_avg_bilin_4hv_8bpp_rvv_i32                     :    4.0    3.5
vp9_avg_bilin_8hv_8bpp_c                           :   38.5   34.2
vp9_avg_bilin_8hv_8bpp_rvv_i32                     :    7.2    6.5
vp9_avg_bilin_16hv_8bpp_c                          :  147.2  130.5
vp9_avg_bilin_16hv_8bpp_rvv_i32                    :   14.5   12.7
vp9_avg_bilin_32hv_8bpp_c                          :  574.2  509.7
vp9_avg_bilin_32hv_8bpp_rvv_i32                    :   42.5   38.0
vp9_avg_bilin_64hv_8bpp_c                          : 2321.2 2017.7
vp9_avg_bilin_64hv_8bpp_rvv_i32                    :  163.5  131.0
vp9_put_bilin_4hv_8bpp_c                           :   10.0    8.7
vp9_put_bilin_4hv_8bpp_rvv_i32                     :    3.5    3.0
vp9_put_bilin_8hv_8bpp_c                           :   35.2   31.2
vp9_put_bilin_8hv_8bpp_rvv_i32                     :    6.5    5.7
vp9_put_bilin_16hv_8bpp_c                          :  134.0  119.0
vp9_put_bilin_16hv_8bpp_rvv_i32                    :   12.7   11.5
vp9_put_bilin_32hv_8bpp_c                          :  538.5  464.2
vp9_put_bilin_32hv_8bpp_rvv_i32                    :   39.7   35.2
vp9_put_bilin_64hv_8bpp_c                          : 2111.7 1833.2
vp9_put_bilin_64hv_8bpp_rvv_i32                    :  138.5  122.5

Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
This commit is contained in:
sunyuechi 2024-08-09 22:24:04 +08:00 committed by Rémi Denis-Courmont
parent 9edd2e723b
commit 4e7b5ac48f
2 changed files with 55 additions and 1 deletions
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46
libavcodec/riscv/vp9_mc_rvv.S
View File

@ -138,6 +138,48 @@ func ff_\op\()_vp9_bilin_64\type\()_rvv, zve32x
endfunc endfunc
.endm .endm
.macro bilin_hv op
func ff_\op\()_vp9_bilin_64hv_rvv, zve32x
lpad 0
vsetvlstatic8 64, t0, 64
.Lbilin_hv\op:
.ifc \op,avg
csrwi vxrm, 0
.endif
neg t1, a5
neg t2, a6
li t3, 8
bilin_load v24, a5, h
1:
addi a4, a4, -2
bilin_load v8, a5, h
vwmulu.vx v16, v8, a6
vwmaccsu.vx v16, t2, v24
vwadd.wx v16, v16, t3
vnsra.wi v16, v16, 4
vadd.vv v12, v16, v24
add t5, a0, a1
bilin_load v24, a5, h
vwmulu.vx v16, v24, a6
vwmaccsu.vx v16, t2, v8
vwadd.wx v16, v16, t3
vnsra.wi v16, v16, 4
vadd.vv v0, v16, v8
.ifc \op,avg
vle8.v v8, (a0)
vle8.v v16, (t5)
vaaddu.vv v12, v12, v8
vaaddu.vv v0, v0, v16
.endif
vse8.v v12, (a0)
vse8.v v0, (t5)
add a0, t5, a1
bnez a4, 1b
ret
endfunc
.endm
.irp len, 64, 32, 16, 8, 4 .irp len, 64, 32, 16, 8, 4
copy_avg \len copy_avg \len
.endr .endr
@ -146,6 +188,8 @@ bilin_h_v put, h, a5
bilin_h_v avg, h, a5 bilin_h_v avg, h, a5
bilin_h_v put, v, a6 bilin_h_v put, v, a6
bilin_h_v avg, v, a6 bilin_h_v avg, v, a6
bilin_hv put
bilin_hv avg
.macro func_bilin_h_v len, op, type .macro func_bilin_h_v len, op, type
func ff_\op\()_vp9_bilin_\len\()\type\()_rvv, zve32x func ff_\op\()_vp9_bilin_\len\()\type\()_rvv, zve32x
@ -157,7 +201,7 @@ endfunc
.irp len, 32, 16, 8, 4 .irp len, 32, 16, 8, 4
.irp op, put, avg .irp op, put, avg
.irp type, h, v .irp type, h, v, hv
func_bilin_h_v \len, \op, \type func_bilin_h_v \len, \op, \type
.endr .endr
.endr .endr

10
libavcodec/riscv/vp9dsp_init.c
View File

@ -83,6 +83,16 @@ static av_cold void vp9dsp_mc_init_riscv(VP9DSPContext *dsp, int bpp)
dsp->mc[4][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_4h_rvv; dsp->mc[4][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_4h_rvv;
dsp->mc[4][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_4v_rvv; dsp->mc[4][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_4v_rvv;
dsp->mc[4][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_4h_rvv; dsp->mc[4][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_4h_rvv;
dsp->mc[0][FILTER_BILINEAR ][0][1][1] = ff_put_vp9_bilin_64hv_rvv;
dsp->mc[0][FILTER_BILINEAR ][1][1][1] = ff_avg_vp9_bilin_64hv_rvv;
dsp->mc[1][FILTER_BILINEAR ][0][1][1] = ff_put_vp9_bilin_32hv_rvv;
dsp->mc[1][FILTER_BILINEAR ][1][1][1] = ff_avg_vp9_bilin_32hv_rvv;
dsp->mc[2][FILTER_BILINEAR ][0][1][1] = ff_put_vp9_bilin_16hv_rvv;
dsp->mc[2][FILTER_BILINEAR ][1][1][1] = ff_avg_vp9_bilin_16hv_rvv;
dsp->mc[3][FILTER_BILINEAR ][0][1][1] = ff_put_vp9_bilin_8hv_rvv;
dsp->mc[3][FILTER_BILINEAR ][1][1][1] = ff_avg_vp9_bilin_8hv_rvv;
dsp->mc[4][FILTER_BILINEAR ][0][1][1] = ff_put_vp9_bilin_4hv_rvv;
dsp->mc[4][FILTER_BILINEAR ][1][1][1] = ff_avg_vp9_bilin_4hv_rvv;
#undef init_fpel #undef init_fpel
} }