From 29b9d616c212f20bc0d3e24928919a14efc047f8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= <remi@remlab.net>
Date: Mon, 17 Jul 2023 20:11:08 +0300
Subject: [PATCH] lavu/float_dsp: rework RISC-V V scalar product

1) Take the reductive sum out of the loop,
   leaving a regular vector addition in the loop.
2) Merge the addition and the multiplication.
3) Unroll.

Before:
scalarproduct_float_rvv_f32: 832.5

After:
scalarproduct_float_rvv_f32: 275.2
---
 libavutil/riscv/float_dsp_rvv.S | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index fa8f9dc212..7cfc890bc2 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -166,20 +166,22 @@ endfunc
 
 // a0 = (a0).(a1) [0..a2-1]
 func ff_scalarproduct_float_rvv, zve32f
-        vsetivli     zero, 1, e32, m1, ta, ma
-        vmv.s.x      v8, zero
+        vsetvli      t0, zero, e32, m8, ta, ma
+        vmv.v.x      v8, zero
+        vmv.s.x      v0, zero
 1:
-        vsetvli      t0, a2, e32, m1, ta, ma
+        vsetvli      t0, a2, e32, m8, tu, ma
         vle32.v      v16, (a0)
         sub          a2, a2, t0
         vle32.v      v24, (a1)
         sh2add       a0, t0, a0
-        vfmul.vv     v16, v16, v24
+        vfmacc.vv    v8, v16, v24
         sh2add       a1, t0, a1
-        vfredusum.vs v8, v16, v8
         bnez         a2, 1b
 
-        vfmv.f.s fa0, v8
+        vsetvli      t0, zero, e32, m8, ta, ma
+        vfredusum.vs v0, v8, v0
+        vfmv.f.s     fa0, v0
 NOHWF   fmv.x.w  a0, fa0
         ret
 endfunc