mirror of https://git.ffmpeg.org/ffmpeg.git
Fix h264/vp8 intra pred on Athlon XP
Whose idea was it to have a CPU that didn't SIGILL on an invalid instruction? Originally committed as revision 23927 to svn://svn.ffmpeg.org/ffmpeg/trunk
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@ -115,7 +115,7 @@ PRED16x16_H ssse3
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; void pred16x16_dc(uint8_t *src, int stride)
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; void pred16x16_dc(uint8_t *src, int stride)
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;-----------------------------------------------------------------------------
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;-----------------------------------------------------------------------------
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%macro PRED16x16_DC 2
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%macro PRED16x16_DC 1
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cglobal pred16x16_dc_%1, 2,7
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cglobal pred16x16_dc_%1, 2,7
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mov r4, r0
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mov r4, r0
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sub r0, r1
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sub r0, r1
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@ -143,10 +143,6 @@ cglobal pred16x16_dc_%1, 2,7
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movd m0, r2d
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movd m0, r2d
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punpcklbw m0, m0
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punpcklbw m0, m0
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pshufw m0, m0, 0
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pshufw m0, m0, 0
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%elifidn %1, sse
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imul r2d, 0x01010101
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movd m0, r2d
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shufps m0, m0, 0
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%elifidn %1, sse2
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%elifidn %1, sse2
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movd m0, r2d
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movd m0, r2d
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punpcklbw m0, m0
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punpcklbw m0, m0
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@ -161,18 +157,18 @@ cglobal pred16x16_dc_%1, 2,7
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%if mmsize==8
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%if mmsize==8
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mov r3d, 8
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mov r3d, 8
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.loop:
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.loop:
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%2 [r4+r1*0+0], m0
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mova [r4+r1*0+0], m0
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%2 [r4+r1*0+8], m0
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mova [r4+r1*0+8], m0
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%2 [r4+r1*1+0], m0
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mova [r4+r1*1+0], m0
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%2 [r4+r1*1+8], m0
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mova [r4+r1*1+8], m0
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%else
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%else
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mov r3d, 4
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mov r3d, 4
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.loop:
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.loop:
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%2 [r4+r1*0], m0
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mova [r4+r1*0], m0
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%2 [r4+r1*1], m0
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mova [r4+r1*1], m0
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lea r4, [r4+r1*2]
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lea r4, [r4+r1*2]
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%2 [r4+r1*0], m0
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mova [r4+r1*0], m0
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%2 [r4+r1*1], m0
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mova [r4+r1*1], m0
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%endif
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%endif
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lea r4, [r4+r1*2]
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lea r4, [r4+r1*2]
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dec r3d
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dec r3d
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@ -181,11 +177,10 @@ cglobal pred16x16_dc_%1, 2,7
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%endmacro
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%endmacro
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INIT_MMX
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INIT_MMX
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PRED16x16_DC mmxext, movq
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PRED16x16_DC mmxext
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INIT_XMM
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INIT_XMM
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PRED16x16_DC sse, movaps
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PRED16x16_DC sse2
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PRED16x16_DC sse2, movdqa
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PRED16x16_DC ssse3
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PRED16x16_DC ssse3, movdqa
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;-----------------------------------------------------------------------------
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;-----------------------------------------------------------------------------
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; void pred16x16_tm_vp8(uint8_t *src, int stride)
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; void pred16x16_tm_vp8(uint8_t *src, int stride)
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@ -2329,7 +2329,6 @@ void ff_pred16x16_horizontal_mmx (uint8_t *src, int stride);
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void ff_pred16x16_horizontal_mmxext(uint8_t *src, int stride);
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void ff_pred16x16_horizontal_mmxext(uint8_t *src, int stride);
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void ff_pred16x16_horizontal_ssse3 (uint8_t *src, int stride);
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void ff_pred16x16_horizontal_ssse3 (uint8_t *src, int stride);
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void ff_pred16x16_dc_mmxext (uint8_t *src, int stride);
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void ff_pred16x16_dc_mmxext (uint8_t *src, int stride);
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void ff_pred16x16_dc_sse (uint8_t *src, int stride);
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void ff_pred16x16_dc_sse2 (uint8_t *src, int stride);
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void ff_pred16x16_dc_sse2 (uint8_t *src, int stride);
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void ff_pred16x16_dc_ssse3 (uint8_t *src, int stride);
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void ff_pred16x16_dc_ssse3 (uint8_t *src, int stride);
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void ff_pred16x16_tm_vp8_mmx (uint8_t *src, int stride);
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void ff_pred16x16_tm_vp8_mmx (uint8_t *src, int stride);
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@ -2384,7 +2383,6 @@ void ff_h264_pred_init_x86(H264PredContext *h, int codec_id)
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if (mm_flags & FF_MM_SSE) {
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if (mm_flags & FF_MM_SSE) {
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h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_sse;
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h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_sse;
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h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_sse;
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}
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}
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if (mm_flags & FF_MM_SSE2) {
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if (mm_flags & FF_MM_SSE2) {
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