RepoMirrors
/
ffmpeg
mirror of https://git.ffmpeg.org/ffmpeg.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
ffmpeg/libswscale/riscv/rgb2rgb_rvv.S

147 lines
3.5 KiB
ArmAsm
Raw Normal View History

sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
2022-09-28 15:29:59 +00:00
/*
* Copyright © 2022 Rémi Denis-Courmont.
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "libavutil/riscv/asm.S"
func ff_shuffle_bytes_0321_rvv, zve32x
swscale/rgb2rgb2: rework RISC-V V shuffle_bytes_{0321,2103} This avoids strided loads. Before: shuffle_bytes_0321_rvv_i32: 307.7 shuffle_bytes_2103_rvv_i32: 308.7 After: shuffle_bytes_0321_rvv_i32: 59.7 shuffle_bytes_2103_rvv_i32: 61.5
2023-07-18 18:39:59 +00:00
li t1, 0x00ff00ff
j 1f
endfunc
func ff_shuffle_bytes_2103_rvv, zve32x
li t1, ~0x00ff00ff
sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
2022-09-28 15:29:59 +00:00
1:
swscale/rgb2rgb2: rework RISC-V V shuffle_bytes_{0321,2103} This avoids strided loads. Before: shuffle_bytes_0321_rvv_i32: 307.7 shuffle_bytes_2103_rvv_i32: 308.7 After: shuffle_bytes_0321_rvv_i32: 59.7 shuffle_bytes_2103_rvv_i32: 61.5
2023-07-18 18:39:59 +00:00
not t2, t1
sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
2022-09-28 15:29:59 +00:00
srai a2, a2, 2
2:
swscale/rgb2rgb2: rework RISC-V V shuffle_bytes_{0321,2103} This avoids strided loads. Before: shuffle_bytes_0321_rvv_i32: 307.7 shuffle_bytes_2103_rvv_i32: 308.7 After: shuffle_bytes_0321_rvv_i32: 59.7 shuffle_bytes_2103_rvv_i32: 61.5
2023-07-18 18:39:59 +00:00
vsetvli t0, a2, e32, m8, ta, ma
vle32.v v8, (a0)
sub a2, a2, t0
vand.vx v16, v8, t2
sh2add a0, t0, a0
vand.vx v8, v8, t1
vsrl.vi v24, v16, 16
vsll.vi v16, v16, 16
vor.vv v8, v8, v24
vor.vv v8, v16, v8
vse32.v v8, (a1)
sh2add a1, t0, a1
bnez a2, 2b
sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
2022-09-28 15:29:59 +00:00
ret
endfunc
func ff_shuffle_bytes_1230_rvv, zve32x
swscale/rgb2rgb2: rework RISC-V V shuffle_bytes_{1230,3012} This avoids strided loads. Before: shuffle_bytes_1230_rvv_i32: 308.7 shuffle_bytes_3012_rvv_i32: 308.7 After: shuffle_bytes_1230_rvv_i32: 46.7 shuffle_bytes_3012_rvv_i32: 46.7
2023-07-18 17:25:13 +00:00
li t1, 24
li t2, 8
j 3f
sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
2022-09-28 15:29:59 +00:00
endfunc
func ff_shuffle_bytes_3012_rvv, zve32x
swscale/rgb2rgb2: rework RISC-V V shuffle_bytes_{1230,3012} This avoids strided loads. Before: shuffle_bytes_1230_rvv_i32: 308.7 shuffle_bytes_3012_rvv_i32: 308.7 After: shuffle_bytes_1230_rvv_i32: 46.7 shuffle_bytes_3012_rvv_i32: 46.7
2023-07-18 17:25:13 +00:00
li t1, 8
li t2, 24
3:
srai a2, a2, 2
4:
vsetvli t0, a2, e32, m8, ta, ma
vle32.v v8, (a0)
sub a2, a2, t0
vsll.vx v16, v8, t1
sh2add a0, t0, a0
vsrl.vx v8, v8, t2
vor.vv v16, v16, v8
vse32.v v16, (a1)
sh2add a1, t0, a1
bnez a2, 4b
ret
sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
2022-09-28 15:29:59 +00:00
endfunc
sws/rgb2rgb: RISC-V V interleaveBytes
2022-09-28 15:30:00 +00:00
func ff_interleave_bytes_rvv, zve32x
1:
mv t0, a0
mv t1, a1
mv t2, a2
mv t3, a3
addi a4, a4, -1
2:
libswscale/riscv: fix syntax of vsetvli Add missing operand which clang complains about but GCC assumes it to be 'm1' if not specified. Works around build failure with Clang: | src/libswscale/riscv/rgb2rgb_rvv.S:88:25: error: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] | vsetvli t4, t3, e8, ta, ma | ^ Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
2023-07-03 02:44:12 +00:00
vsetvli t4, t3, e8, m1, ta, ma
sws/rgb2rgb: RISC-V V interleaveBytes
2022-09-28 15:30:00 +00:00
sub t3, t3, t4
vle8.v v8, (t0)
add t0, t4, t0
vle8.v v9, (t1)
add t1, t4, t1
vsseg2e8.v v8, (t2)
sh1add t2, t4, t2
bnez t4, 2b
add a0, a0, a5
add a1, a1, a6
add a2, a2, a7
bnez a4, 1b
ret
endfunc
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
.macro yuy2_to_i422p y_shift
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
addi a4, a4, 1
swscale/rgb2rgb: avoid S-regs in RISC-V V uyvytoyuv422 We can make do with callee-clobbered registers only now. As an added bonus, this makes the code XLEN-independent.
2023-09-29 19:36:16 +00:00
lw t6, (sp)
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
srai a4, a4, 1 // pixel width -> chroma width
1:
mv t4, a4
mv t3, a3
mv t0, a0
mv t1, a1
mv t2, a2
addi a5, a5, -1
2:
vsetvli t5, t4, e8, m1, ta, ma
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
vlseg2e16.v v16, (t3)
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
sub t4, t4, t5
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
vnsrl.wi v24, v16, \y_shift // Y0
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
sh2add t3, t5, t3
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
vnsrl.wi v25, v18, \y_shift // Y1
vnsrl.wi v28, v16, 8 - \y_shift // U
vnsrl.wi v30, v18, 8 - \y_shift // V
vsseg2e8.v v24, (t0)
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
sh1add t0, t5, t0
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
vse8.v v28, (t1)
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
add t1, t5, t1
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
vse8.v v30, (t2)
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
add t2, t5, t2
bnez t4, 2b
swscale/rgb2rgb: avoid S-regs in RISC-V V uyvytoyuv422 We can make do with callee-clobbered registers only now. As an added bonus, this makes the code XLEN-independent.
2023-09-29 19:36:16 +00:00
add a3, a3, t6
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
add a0, a0, a6
add a1, a1, a7
add a2, a2, a7
bnez a5, 1b
ret
.endm
func ff_uyvytoyuv422_rvv, zve32x
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
yuy2_to_i422p 8
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
endfunc
func ff_yuyvtoyuv422_rvv, zve32x
swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 This avoids using relatively slow register strides.
2023-09-29 19:36:16 +00:00
yuy2_to_i422p 0
sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
2022-09-28 15:30:01 +00:00
endfunc