2014-11-29 23:04:37 +00:00
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/*
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2016-08-28 17:51:22 +00:00
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* H.264/HEVC hardware encoding using nvidia nvenc
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* Copyright (c) 2016 Timo Rothenpieler <timo@rothenpieler.org>
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2014-11-29 23:04:37 +00:00
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2016-05-25 13:04:28 +00:00
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#include "config.h"
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2016-10-10 10:55:59 +00:00
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#include "nvenc.h"
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2014-11-29 23:04:37 +00:00
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2016-10-10 10:55:59 +00:00
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#include "libavutil/hwcontext_cuda.h"
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2016-05-29 12:23:26 +00:00
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#include "libavutil/hwcontext.h"
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2014-11-29 23:04:37 +00:00
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#include "libavutil/imgutils.h"
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#include "libavutil/avassert.h"
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#include "libavutil/mem.h"
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2016-11-25 19:11:45 +00:00
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#include "libavutil/pixdesc.h"
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2014-11-29 23:04:37 +00:00
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#include "internal.h"
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2016-05-20 22:08:06 +00:00
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2016-05-29 12:23:26 +00:00
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#define NVENC_CAP 0x30
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2016-05-25 16:39:54 +00:00
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#define IS_CBR(rc) (rc == NV_ENC_PARAMS_RC_CBR || \
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rc == NV_ENC_PARAMS_RC_2_PASS_QUALITY || \
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rc == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP)
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2016-05-25 13:04:28 +00:00
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const enum AVPixelFormat ff_nvenc_pix_fmts[] = {
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AV_PIX_FMT_YUV420P,
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AV_PIX_FMT_NV12,
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2016-08-25 15:18:03 +00:00
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AV_PIX_FMT_P010,
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2016-05-25 13:04:28 +00:00
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AV_PIX_FMT_YUV444P,
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2016-08-25 15:18:03 +00:00
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AV_PIX_FMT_YUV444P16,
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2016-09-07 13:35:14 +00:00
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AV_PIX_FMT_0RGB32,
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AV_PIX_FMT_0BGR32,
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2016-05-25 13:04:28 +00:00
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AV_PIX_FMT_CUDA,
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AV_PIX_FMT_NONE
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};
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2014-11-29 23:04:37 +00:00
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2016-08-25 15:18:03 +00:00
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#define IS_10BIT(pix_fmt) (pix_fmt == AV_PIX_FMT_P010 || \
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pix_fmt == AV_PIX_FMT_YUV444P16)
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#define IS_YUV444(pix_fmt) (pix_fmt == AV_PIX_FMT_YUV444P || \
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pix_fmt == AV_PIX_FMT_YUV444P16)
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2016-05-20 15:37:00 +00:00
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static const struct {
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NVENCSTATUS nverr;
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int averr;
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const char *desc;
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} nvenc_errors[] = {
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{ NV_ENC_SUCCESS, 0, "success" },
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{ NV_ENC_ERR_NO_ENCODE_DEVICE, AVERROR(ENOENT), "no encode device" },
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{ NV_ENC_ERR_UNSUPPORTED_DEVICE, AVERROR(ENOSYS), "unsupported device" },
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{ NV_ENC_ERR_INVALID_ENCODERDEVICE, AVERROR(EINVAL), "invalid encoder device" },
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{ NV_ENC_ERR_INVALID_DEVICE, AVERROR(EINVAL), "invalid device" },
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{ NV_ENC_ERR_DEVICE_NOT_EXIST, AVERROR(EIO), "device does not exist" },
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{ NV_ENC_ERR_INVALID_PTR, AVERROR(EFAULT), "invalid ptr" },
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{ NV_ENC_ERR_INVALID_EVENT, AVERROR(EINVAL), "invalid event" },
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{ NV_ENC_ERR_INVALID_PARAM, AVERROR(EINVAL), "invalid param" },
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{ NV_ENC_ERR_INVALID_CALL, AVERROR(EINVAL), "invalid call" },
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{ NV_ENC_ERR_OUT_OF_MEMORY, AVERROR(ENOMEM), "out of memory" },
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{ NV_ENC_ERR_ENCODER_NOT_INITIALIZED, AVERROR(EINVAL), "encoder not initialized" },
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{ NV_ENC_ERR_UNSUPPORTED_PARAM, AVERROR(ENOSYS), "unsupported param" },
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{ NV_ENC_ERR_LOCK_BUSY, AVERROR(EAGAIN), "lock busy" },
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2016-09-24 18:31:00 +00:00
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{ NV_ENC_ERR_NOT_ENOUGH_BUFFER, AVERROR_BUFFER_TOO_SMALL, "not enough buffer"},
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2016-05-20 15:37:00 +00:00
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{ NV_ENC_ERR_INVALID_VERSION, AVERROR(EINVAL), "invalid version" },
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{ NV_ENC_ERR_MAP_FAILED, AVERROR(EIO), "map failed" },
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{ NV_ENC_ERR_NEED_MORE_INPUT, AVERROR(EAGAIN), "need more input" },
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{ NV_ENC_ERR_ENCODER_BUSY, AVERROR(EAGAIN), "encoder busy" },
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{ NV_ENC_ERR_EVENT_NOT_REGISTERD, AVERROR(EBADF), "event not registered" },
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{ NV_ENC_ERR_GENERIC, AVERROR_UNKNOWN, "generic error" },
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{ NV_ENC_ERR_INCOMPATIBLE_CLIENT_KEY, AVERROR(EINVAL), "incompatible client key" },
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{ NV_ENC_ERR_UNIMPLEMENTED, AVERROR(ENOSYS), "unimplemented" },
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{ NV_ENC_ERR_RESOURCE_REGISTER_FAILED, AVERROR(EIO), "resource register failed" },
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{ NV_ENC_ERR_RESOURCE_NOT_REGISTERED, AVERROR(EBADF), "resource not registered" },
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{ NV_ENC_ERR_RESOURCE_NOT_MAPPED, AVERROR(EBADF), "resource not mapped" },
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};
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static int nvenc_map_error(NVENCSTATUS err, const char **desc)
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{
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int i;
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for (i = 0; i < FF_ARRAY_ELEMS(nvenc_errors); i++) {
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if (nvenc_errors[i].nverr == err) {
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if (desc)
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*desc = nvenc_errors[i].desc;
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return nvenc_errors[i].averr;
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}
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}
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if (desc)
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*desc = "unknown error";
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return AVERROR_UNKNOWN;
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}
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static int nvenc_print_error(void *log_ctx, NVENCSTATUS err,
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const char *error_string)
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{
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const char *desc;
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int ret;
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ret = nvenc_map_error(err, &desc);
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av_log(log_ctx, AV_LOG_ERROR, "%s: %s (%d)\n", error_string, desc, err);
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return ret;
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}
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2016-05-29 12:23:26 +00:00
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static av_cold int nvenc_load_libraries(AVCodecContext *avctx)
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2014-11-29 23:04:37 +00:00
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{
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NvencContext *ctx = avctx->priv_data;
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NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
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2016-05-29 12:23:26 +00:00
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NVENCSTATUS err;
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2016-08-28 17:46:44 +00:00
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uint32_t nvenc_max_ver;
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2016-10-10 10:55:59 +00:00
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int ret;
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ret = cuda_load_functions(&dl_fn->cuda_dl);
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if (ret < 0)
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return ret;
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ret = nvenc_load_functions(&dl_fn->nvenc_dl);
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if (ret < 0)
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return ret;
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2014-11-29 23:04:37 +00:00
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2016-10-10 10:55:59 +00:00
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err = dl_fn->nvenc_dl->NvEncodeAPIGetMaxSupportedVersion(&nvenc_max_ver);
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2016-08-28 17:46:44 +00:00
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if (err != NV_ENC_SUCCESS)
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return nvenc_print_error(avctx, err, "Failed to query nvenc max version");
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av_log(avctx, AV_LOG_VERBOSE, "Loaded Nvenc version %d.%d\n", nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
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if ((NVENCAPI_MAJOR_VERSION << 4 | NVENCAPI_MINOR_VERSION) > nvenc_max_ver) {
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av_log(avctx, AV_LOG_ERROR, "Driver does not support the required nvenc API version. "
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"Required: %d.%d Found: %d.%d\n",
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NVENCAPI_MAJOR_VERSION, NVENCAPI_MINOR_VERSION,
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nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
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return AVERROR(ENOSYS);
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}
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2016-05-29 12:23:26 +00:00
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dl_fn->nvenc_funcs.version = NV_ENCODE_API_FUNCTION_LIST_VER;
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2014-11-29 23:04:37 +00:00
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2016-10-10 10:55:59 +00:00
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err = dl_fn->nvenc_dl->NvEncodeAPICreateInstance(&dl_fn->nvenc_funcs);
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2016-05-29 12:23:26 +00:00
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if (err != NV_ENC_SUCCESS)
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return nvenc_print_error(avctx, err, "Failed to create nvenc instance");
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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av_log(avctx, AV_LOG_VERBOSE, "Nvenc initialized successfully\n");
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2014-11-29 23:04:37 +00:00
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return 0;
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}
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2016-05-29 12:23:26 +00:00
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static av_cold int nvenc_open_session(AVCodecContext *avctx)
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2014-11-29 23:04:37 +00:00
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{
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2016-05-29 12:23:26 +00:00
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NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS params = { 0 };
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NvencContext *ctx = avctx->priv_data;
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NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
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NVENCSTATUS ret;
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params.version = NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS_VER;
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params.apiVersion = NVENCAPI_VERSION;
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params.device = ctx->cu_context;
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params.deviceType = NV_ENC_DEVICE_TYPE_CUDA;
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ret = p_nvenc->nvEncOpenEncodeSessionEx(¶ms, &ctx->nvencoder);
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if (ret != NV_ENC_SUCCESS) {
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ctx->nvencoder = NULL;
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return nvenc_print_error(avctx, ret, "OpenEncodeSessionEx failed");
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2014-11-29 23:04:37 +00:00
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}
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2016-05-29 12:23:26 +00:00
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return 0;
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2014-11-29 23:04:37 +00:00
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}
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2016-05-29 12:23:26 +00:00
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static int nvenc_check_codec_support(AVCodecContext *avctx)
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2014-11-29 23:04:37 +00:00
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{
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NvencContext *ctx = avctx->priv_data;
|
2016-05-29 12:23:26 +00:00
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NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
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int i, ret, count = 0;
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GUID *guids = NULL;
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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ret = p_nvenc->nvEncGetEncodeGUIDCount(ctx->nvencoder, &count);
|
2015-03-24 04:34:59 +00:00
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2016-05-29 12:23:26 +00:00
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if (ret != NV_ENC_SUCCESS || !count)
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return AVERROR(ENOSYS);
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2016-05-25 10:15:03 +00:00
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2016-05-29 12:23:26 +00:00
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guids = av_malloc(count * sizeof(GUID));
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if (!guids)
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return AVERROR(ENOMEM);
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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ret = p_nvenc->nvEncGetEncodeGUIDs(ctx->nvencoder, guids, count, &count);
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if (ret != NV_ENC_SUCCESS) {
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ret = AVERROR(ENOSYS);
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goto fail;
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}
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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ret = AVERROR(ENOSYS);
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for (i = 0; i < count; i++) {
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if (!memcmp(&guids[i], &ctx->init_encode_params.encodeGUID, sizeof(*guids))) {
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ret = 0;
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break;
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}
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}
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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fail:
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av_free(guids);
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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return ret;
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}
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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static int nvenc_check_cap(AVCodecContext *avctx, NV_ENC_CAPS cap)
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{
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NvencContext *ctx = avctx->priv_data;
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NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
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NV_ENC_CAPS_PARAM params = { 0 };
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int ret, val = 0;
|
2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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params.version = NV_ENC_CAPS_PARAM_VER;
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params.capsToQuery = cap;
|
2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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ret = p_nvenc->nvEncGetEncodeCaps(ctx->nvencoder, ctx->init_encode_params.encodeGUID, ¶ms, &val);
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
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if (ret == NV_ENC_SUCCESS)
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return val;
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return 0;
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}
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2014-11-29 23:04:37 +00:00
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2016-05-29 12:23:26 +00:00
|
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static int nvenc_check_capabilities(AVCodecContext *avctx)
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{
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NvencContext *ctx = avctx->priv_data;
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int ret;
|
2014-11-29 23:04:37 +00:00
|
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|
2016-05-29 12:23:26 +00:00
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ret = nvenc_check_codec_support(avctx);
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|
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if (ret < 0) {
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av_log(avctx, AV_LOG_VERBOSE, "Codec not supported\n");
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|
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return ret;
|
2014-11-29 23:04:37 +00:00
|
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}
|
|
|
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|
2016-05-29 12:23:26 +00:00
|
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ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_YUV444_ENCODE);
|
2016-08-25 15:18:03 +00:00
|
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|
if (IS_YUV444(ctx->data_pix_fmt) && ret <= 0) {
|
2016-05-29 12:23:26 +00:00
|
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|
av_log(avctx, AV_LOG_VERBOSE, "YUV444P not supported\n");
|
|
|
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return AVERROR(ENOSYS);
|
2014-11-29 23:04:37 +00:00
|
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}
|
|
|
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|
2016-05-29 12:23:26 +00:00
|
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ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOSSLESS_ENCODE);
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|
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if (ctx->preset >= PRESET_LOSSLESS_DEFAULT && ret <= 0) {
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av_log(avctx, AV_LOG_VERBOSE, "Lossless encoding not supported\n");
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return AVERROR(ENOSYS);
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|
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}
|
2014-11-29 23:04:37 +00:00
|
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|
2016-05-29 12:23:26 +00:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_WIDTH_MAX);
|
|
|
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if (ret < avctx->width) {
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|
|
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av_log(avctx, AV_LOG_VERBOSE, "Width %d exceeds %d\n",
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|
|
avctx->width, ret);
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|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_HEIGHT_MAX);
|
|
|
|
if (ret < avctx->height) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Height %d exceeds %d\n",
|
|
|
|
avctx->height, ret);
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_NUM_MAX_BFRAMES);
|
|
|
|
if (ret < avctx->max_b_frames) {
|
2016-04-27 17:45:23 +00:00
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Max B-frames %d exceed %d\n",
|
2016-05-29 12:23:26 +00:00
|
|
|
avctx->max_b_frames, ret);
|
|
|
|
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-06-06 19:19:29 +00:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_FIELD_ENCODING);
|
|
|
|
if (ret < 1 && avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"Interlaced encoding is not supported. Supported level: %d\n",
|
|
|
|
ret);
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-08-25 15:18:03 +00:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_10BIT_ENCODE);
|
|
|
|
if (IS_10BIT(ctx->data_pix_fmt) && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "10 bit encode not supported\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-08-25 15:20:03 +00:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOOKAHEAD);
|
|
|
|
if (ctx->rc_lookahead > 0 && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "RC lookahead not supported\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-10-14 15:02:54 +00:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_TEMPORAL_AQ);
|
|
|
|
if (ctx->temporal_aq > 0 && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ not supported\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
static av_cold int nvenc_check_device(AVCodecContext *avctx, int idx)
|
2014-11-29 23:04:37 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
2016-05-29 12:23:26 +00:00
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
char name[128] = { 0};
|
|
|
|
int major, minor, ret;
|
|
|
|
CUresult cu_res;
|
|
|
|
CUdevice cu_device;
|
|
|
|
CUcontext dummy;
|
|
|
|
int loglevel = AV_LOG_VERBOSE;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if (ctx->device == LIST_DEVICES)
|
|
|
|
loglevel = AV_LOG_INFO;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuDeviceGet(&cu_device, idx);
|
2016-05-29 12:23:26 +00:00
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR,
|
|
|
|
"Cannot access the CUDA device %d\n",
|
|
|
|
idx);
|
|
|
|
return -1;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuDeviceGetName(name, sizeof(name), cu_device);
|
2017-01-18 22:22:28 +00:00
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "cuDeviceGetName failed on device %d\n", idx);
|
2016-05-29 12:23:26 +00:00
|
|
|
return -1;
|
2017-01-18 22:22:28 +00:00
|
|
|
}
|
2016-05-29 12:23:26 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuDeviceComputeCapability(&major, &minor, cu_device);
|
2017-01-18 22:22:28 +00:00
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "cuDeviceComputeCapability failed on device %d\n", idx);
|
2016-05-29 12:23:26 +00:00
|
|
|
return -1;
|
2017-01-18 22:22:28 +00:00
|
|
|
}
|
2016-05-29 12:23:26 +00:00
|
|
|
|
|
|
|
av_log(avctx, loglevel, "[ GPU #%d - < %s > has Compute SM %d.%d ]\n", idx, name, major, minor);
|
|
|
|
if (((major << 4) | minor) < NVENC_CAP) {
|
|
|
|
av_log(avctx, loglevel, "does not support NVENC\n");
|
|
|
|
goto fail;
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
2017-01-18 22:01:28 +00:00
|
|
|
if (ctx->device != idx && ctx->device != ANY_DEVICE)
|
|
|
|
return -1;
|
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuCtxCreate(&ctx->cu_context_internal, 0, cu_device);
|
2016-05-29 12:23:26 +00:00
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Failed creating CUDA context for NVENC: 0x%x\n", (int)cu_res);
|
|
|
|
goto fail;
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
ctx->cu_context = ctx->cu_context_internal;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
|
2016-05-29 12:23:26 +00:00
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Failed popping CUDA context: 0x%x\n", (int)cu_res);
|
|
|
|
goto fail2;
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_open_session(avctx)) < 0)
|
|
|
|
goto fail2;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_check_capabilities(avctx)) < 0)
|
|
|
|
goto fail3;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
av_log(avctx, loglevel, "supports NVENC\n");
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
dl_fn->nvenc_device_count++;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2017-01-18 22:01:28 +00:00
|
|
|
if (ctx->device == idx || ctx->device == ANY_DEVICE)
|
2016-05-29 12:23:26 +00:00
|
|
|
return 0;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
fail3:
|
|
|
|
p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
|
|
|
|
ctx->nvencoder = NULL;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
fail2:
|
2016-10-10 10:55:59 +00:00
|
|
|
dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal);
|
2016-05-29 12:23:26 +00:00
|
|
|
ctx->cu_context_internal = NULL;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
fail:
|
|
|
|
return AVERROR(ENOSYS);
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
static av_cold int nvenc_setup_device(AVCodecContext *avctx)
|
2014-11-29 23:04:37 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
|
|
|
ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_H264_GUID;
|
|
|
|
break;
|
|
|
|
case AV_CODEC_ID_HEVC:
|
|
|
|
ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_HEVC_GUID;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return AVERROR_BUG;
|
|
|
|
}
|
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
2016-05-29 12:23:26 +00:00
|
|
|
AVHWFramesContext *frames_ctx;
|
2016-05-20 22:08:06 +00:00
|
|
|
AVCUDADeviceContext *device_hwctx;
|
2016-05-29 12:23:26 +00:00
|
|
|
int ret;
|
2016-05-20 22:08:06 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if (!avctx->hw_frames_ctx)
|
2016-05-20 22:08:06 +00:00
|
|
|
return AVERROR(EINVAL);
|
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
|
2016-05-20 22:08:06 +00:00
|
|
|
device_hwctx = frames_ctx->device_ctx->hwctx;
|
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
ctx->cu_context = device_hwctx->cuda_ctx;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
ret = nvenc_open_session(avctx);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
ret = nvenc_check_capabilities(avctx);
|
|
|
|
if (ret < 0) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Provided device doesn't support required NVENC features\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
int i, nb_devices = 0;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
if ((dl_fn->cuda_dl->cuInit(0)) != CUDA_SUCCESS) {
|
2016-05-29 12:23:26 +00:00
|
|
|
av_log(avctx, AV_LOG_ERROR,
|
|
|
|
"Cannot init CUDA\n");
|
|
|
|
return AVERROR_UNKNOWN;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
if ((dl_fn->cuda_dl->cuDeviceGetCount(&nb_devices)) != CUDA_SUCCESS) {
|
2016-05-29 12:23:26 +00:00
|
|
|
av_log(avctx, AV_LOG_ERROR,
|
|
|
|
"Cannot enumerate the CUDA devices\n");
|
|
|
|
return AVERROR_UNKNOWN;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if (!nb_devices) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "No CUDA capable devices found\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
2016-05-20 22:08:06 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "%d CUDA capable devices found\n", nb_devices);
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
dl_fn->nvenc_device_count = 0;
|
|
|
|
for (i = 0; i < nb_devices; ++i) {
|
|
|
|
if ((nvenc_check_device(avctx, i)) >= 0 && ctx->device != LIST_DEVICES)
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if (ctx->device == LIST_DEVICES)
|
|
|
|
return AVERROR_EXIT;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if (!dl_fn->nvenc_device_count) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "No NVENC capable devices found\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2017-01-18 22:01:28 +00:00
|
|
|
av_log(avctx, AV_LOG_FATAL, "Requested GPU %d, but only %d GPUs are available!\n", ctx->device, nb_devices);
|
2016-05-29 12:23:26 +00:00
|
|
|
return AVERROR(EINVAL);
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
typedef struct GUIDTuple {
|
|
|
|
const GUID guid;
|
|
|
|
int flags;
|
|
|
|
} GUIDTuple;
|
|
|
|
|
2016-09-28 11:52:47 +00:00
|
|
|
#define PRESET_ALIAS(alias, name, ...) \
|
|
|
|
[PRESET_ ## alias] = { NV_ENC_PRESET_ ## name ## _GUID, __VA_ARGS__ }
|
|
|
|
|
|
|
|
#define PRESET(name, ...) PRESET_ALIAS(name, name, __VA_ARGS__)
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
static void nvenc_map_preset(NvencContext *ctx)
|
|
|
|
{
|
|
|
|
GUIDTuple presets[] = {
|
2016-09-28 11:52:47 +00:00
|
|
|
PRESET(DEFAULT),
|
|
|
|
PRESET(HP),
|
|
|
|
PRESET(HQ),
|
|
|
|
PRESET(BD),
|
|
|
|
PRESET_ALIAS(SLOW, HQ, NVENC_TWO_PASSES),
|
|
|
|
PRESET_ALIAS(MEDIUM, HQ, NVENC_ONE_PASS),
|
|
|
|
PRESET_ALIAS(FAST, HP, NVENC_ONE_PASS),
|
|
|
|
PRESET(LOW_LATENCY_DEFAULT, NVENC_LOWLATENCY),
|
|
|
|
PRESET(LOW_LATENCY_HP, NVENC_LOWLATENCY),
|
|
|
|
PRESET(LOW_LATENCY_HQ, NVENC_LOWLATENCY),
|
|
|
|
PRESET(LOSSLESS_DEFAULT, NVENC_LOSSLESS),
|
|
|
|
PRESET(LOSSLESS_HP, NVENC_LOSSLESS),
|
2016-05-25 14:05:50 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
GUIDTuple *t = &presets[ctx->preset];
|
|
|
|
|
|
|
|
ctx->init_encode_params.presetGUID = t->guid;
|
|
|
|
ctx->flags = t->flags;
|
|
|
|
}
|
|
|
|
|
2016-09-28 11:52:47 +00:00
|
|
|
#undef PRESET
|
|
|
|
#undef PRESET_ALIAS
|
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
static av_cold void set_constqp(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 16:39:54 +00:00
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
|
|
|
|
|
|
|
rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
|
2017-03-17 04:12:25 +00:00
|
|
|
|
|
|
|
if (ctx->init_qp_p >= 0) {
|
|
|
|
rc->constQP.qpInterP = ctx->init_qp_p;
|
|
|
|
if (ctx->init_qp_i >= 0 && ctx->init_qp_b >= 0) {
|
|
|
|
rc->constQP.qpIntra = ctx->init_qp_i;
|
|
|
|
rc->constQP.qpInterB = ctx->init_qp_b;
|
|
|
|
} else if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
|
|
|
|
rc->constQP.qpIntra = av_clip(
|
|
|
|
rc->constQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
|
|
|
|
rc->constQP.qpInterB = av_clip(
|
|
|
|
rc->constQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
|
|
|
|
} else {
|
|
|
|
rc->constQP.qpIntra = rc->constQP.qpInterP;
|
|
|
|
rc->constQP.qpInterB = rc->constQP.qpInterP;
|
|
|
|
}
|
|
|
|
} else if (avctx->global_quality > 0) {
|
|
|
|
rc->constQP.qpInterP = avctx->global_quality;
|
|
|
|
rc->constQP.qpInterB = avctx->global_quality;
|
|
|
|
rc->constQP.qpIntra = avctx->global_quality;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
avctx->qmin = -1;
|
|
|
|
avctx->qmax = -1;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold void set_vbr(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 16:39:54 +00:00
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
|
|
|
int qp_inter_p;
|
|
|
|
|
|
|
|
if (avctx->qmin >= 0 && avctx->qmax >= 0) {
|
|
|
|
rc->enableMinQP = 1;
|
|
|
|
rc->enableMaxQP = 1;
|
|
|
|
|
|
|
|
rc->minQP.qpInterB = avctx->qmin;
|
|
|
|
rc->minQP.qpInterP = avctx->qmin;
|
|
|
|
rc->minQP.qpIntra = avctx->qmin;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
rc->maxQP.qpInterB = avctx->qmax;
|
|
|
|
rc->maxQP.qpInterP = avctx->qmax;
|
|
|
|
rc->maxQP.qpIntra = avctx->qmax;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
qp_inter_p = (avctx->qmax + 3 * avctx->qmin) / 4; // biased towards Qmin
|
2016-05-31 15:00:07 +00:00
|
|
|
} else if (avctx->qmin >= 0) {
|
|
|
|
rc->enableMinQP = 1;
|
|
|
|
|
|
|
|
rc->minQP.qpInterB = avctx->qmin;
|
|
|
|
rc->minQP.qpInterP = avctx->qmin;
|
|
|
|
rc->minQP.qpIntra = avctx->qmin;
|
|
|
|
|
|
|
|
qp_inter_p = avctx->qmin;
|
2016-05-25 16:39:54 +00:00
|
|
|
} else {
|
|
|
|
qp_inter_p = 26; // default to 26
|
|
|
|
}
|
|
|
|
|
|
|
|
rc->enableInitialRCQP = 1;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2017-02-28 05:39:12 +00:00
|
|
|
if (ctx->init_qp_p < 0) {
|
|
|
|
rc->initialRCQP.qpInterP = qp_inter_p;
|
2016-05-25 16:39:54 +00:00
|
|
|
} else {
|
2017-02-28 05:39:12 +00:00
|
|
|
rc->initialRCQP.qpInterP = ctx->init_qp_p;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->init_qp_i < 0) {
|
|
|
|
if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
|
|
|
|
rc->initialRCQP.qpIntra = av_clip(
|
|
|
|
rc->initialRCQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
|
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpIntra = rc->initialRCQP.qpInterP;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpIntra = ctx->init_qp_i;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->init_qp_b < 0) {
|
|
|
|
if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
|
|
|
|
rc->initialRCQP.qpInterB = av_clip(
|
|
|
|
rc->initialRCQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
|
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpInterB = rc->initialRCQP.qpInterP;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpInterB = ctx->init_qp_b;
|
2016-05-25 16:39:54 +00:00
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold void set_lossless(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 16:39:54 +00:00
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
|
|
|
|
rc->constQP.qpInterB = 0;
|
|
|
|
rc->constQP.qpInterP = 0;
|
|
|
|
rc->constQP.qpIntra = 0;
|
|
|
|
|
|
|
|
avctx->qmin = -1;
|
|
|
|
avctx->qmax = -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvenc_override_rate_control(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
|
|
|
|
|
|
|
switch (ctx->rc) {
|
|
|
|
case NV_ENC_PARAMS_RC_CONSTQP:
|
|
|
|
set_constqp(avctx);
|
|
|
|
return;
|
|
|
|
case NV_ENC_PARAMS_RC_VBR_MINQP:
|
|
|
|
if (avctx->qmin < 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"The variable bitrate rate-control requires "
|
|
|
|
"the 'qmin' option set.\n");
|
|
|
|
set_vbr(avctx);
|
|
|
|
return;
|
|
|
|
}
|
2017-02-24 01:42:27 +00:00
|
|
|
/* fall through */
|
|
|
|
case NV_ENC_PARAMS_RC_2_PASS_VBR:
|
|
|
|
case NV_ENC_PARAMS_RC_VBR:
|
2016-05-25 16:39:54 +00:00
|
|
|
set_vbr(avctx);
|
|
|
|
break;
|
|
|
|
case NV_ENC_PARAMS_RC_CBR:
|
|
|
|
case NV_ENC_PARAMS_RC_2_PASS_QUALITY:
|
|
|
|
case NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP:
|
2016-05-31 14:55:24 +00:00
|
|
|
break;
|
2016-05-25 16:39:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
rc->rateControlMode = ctx->rc;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 11:17:43 +00:00
|
|
|
static av_cold int nvenc_recalc_surfaces(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
int nb_surfaces = 0;
|
|
|
|
|
|
|
|
if (ctx->rc_lookahead > 0) {
|
|
|
|
nb_surfaces = ctx->rc_lookahead + ((ctx->encode_config.frameIntervalP > 0) ? ctx->encode_config.frameIntervalP : 0) + 1 + 4;
|
|
|
|
if (ctx->nb_surfaces < nb_surfaces) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"Defined rc_lookahead requires more surfaces, "
|
|
|
|
"increasing used surfaces %d -> %d\n", ctx->nb_surfaces, nb_surfaces);
|
|
|
|
ctx->nb_surfaces = nb_surfaces;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->nb_surfaces = FFMAX(1, FFMIN(MAX_REGISTERED_FRAMES, ctx->nb_surfaces));
|
|
|
|
ctx->async_depth = FFMIN(ctx->async_depth, ctx->nb_surfaces - 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
static av_cold void nvenc_setup_rate_control(AVCodecContext *avctx)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
|
|
|
if (avctx->bit_rate > 0) {
|
|
|
|
ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate;
|
|
|
|
} else if (ctx->encode_config.rcParams.averageBitRate > 0) {
|
|
|
|
ctx->encode_config.rcParams.maxBitRate = ctx->encode_config.rcParams.averageBitRate;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (avctx->rc_max_rate > 0)
|
|
|
|
ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate;
|
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
if (ctx->rc < 0) {
|
|
|
|
if (ctx->flags & NVENC_ONE_PASS)
|
|
|
|
ctx->twopass = 0;
|
|
|
|
if (ctx->flags & NVENC_TWO_PASSES)
|
|
|
|
ctx->twopass = 1;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
if (ctx->twopass < 0)
|
|
|
|
ctx->twopass = (ctx->flags & NVENC_LOWLATENCY) != 0;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
if (ctx->cbr) {
|
2016-05-20 14:49:24 +00:00
|
|
|
if (ctx->twopass) {
|
2016-05-25 16:39:54 +00:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_2_PASS_QUALITY;
|
2016-05-20 14:49:24 +00:00
|
|
|
} else {
|
2016-05-25 16:39:54 +00:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CBR;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2016-05-25 16:39:54 +00:00
|
|
|
} else if (avctx->global_quality > 0) {
|
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CONSTQP;
|
|
|
|
} else if (ctx->twopass) {
|
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_2_PASS_VBR;
|
|
|
|
} else if (avctx->qmin >= 0 && avctx->qmax >= 0) {
|
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_VBR_MINQP;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2016-05-25 16:39:54 +00:00
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
if (ctx->flags & NVENC_LOSSLESS) {
|
|
|
|
set_lossless(avctx);
|
2016-05-31 14:53:38 +00:00
|
|
|
} else if (ctx->rc >= 0) {
|
2016-05-25 16:39:54 +00:00
|
|
|
nvenc_override_rate_control(avctx);
|
|
|
|
} else {
|
|
|
|
ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR;
|
|
|
|
set_vbr(avctx);
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (avctx->rc_buffer_size > 0) {
|
|
|
|
ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size;
|
|
|
|
} else if (ctx->encode_config.rcParams.averageBitRate > 0) {
|
|
|
|
ctx->encode_config.rcParams.vbvBufferSize = 2 * ctx->encode_config.rcParams.averageBitRate;
|
|
|
|
}
|
2016-08-25 15:20:03 +00:00
|
|
|
|
2016-09-24 15:55:00 +00:00
|
|
|
if (ctx->aq) {
|
|
|
|
ctx->encode_config.rcParams.enableAQ = 1;
|
|
|
|
ctx->encode_config.rcParams.aqStrength = ctx->aq_strength;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "AQ enabled.\n");
|
2016-08-25 15:20:03 +00:00
|
|
|
}
|
2016-09-24 15:55:00 +00:00
|
|
|
|
|
|
|
if (ctx->temporal_aq) {
|
|
|
|
ctx->encode_config.rcParams.enableTemporalAQ = 1;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ enabled.\n");
|
|
|
|
}
|
|
|
|
|
2016-12-26 07:49:16 +00:00
|
|
|
if (ctx->rc_lookahead > 0) {
|
2016-09-24 15:55:00 +00:00
|
|
|
int lkd_bound = FFMIN(ctx->nb_surfaces, ctx->async_depth) -
|
|
|
|
ctx->encode_config.frameIntervalP - 4;
|
|
|
|
|
|
|
|
if (lkd_bound < 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"Lookahead not enabled. Increase buffer delay (-delay).\n");
|
|
|
|
} else {
|
|
|
|
ctx->encode_config.rcParams.enableLookahead = 1;
|
|
|
|
ctx->encode_config.rcParams.lookaheadDepth = av_clip(ctx->rc_lookahead, 0, lkd_bound);
|
|
|
|
ctx->encode_config.rcParams.disableIadapt = ctx->no_scenecut;
|
|
|
|
ctx->encode_config.rcParams.disableBadapt = !ctx->b_adapt;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"Lookahead enabled: depth %d, scenecut %s, B-adapt %s.\n",
|
|
|
|
ctx->encode_config.rcParams.lookaheadDepth,
|
|
|
|
ctx->encode_config.rcParams.disableIadapt ? "disabled" : "enabled",
|
|
|
|
ctx->encode_config.rcParams.disableBadapt ? "disabled" : "enabled");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->strict_gop) {
|
|
|
|
ctx->encode_config.rcParams.strictGOPTarget = 1;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Strict GOP target enabled.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->nonref_p)
|
|
|
|
ctx->encode_config.rcParams.enableNonRefP = 1;
|
|
|
|
|
|
|
|
if (ctx->zerolatency)
|
|
|
|
ctx->encode_config.rcParams.zeroReorderDelay = 1;
|
|
|
|
|
|
|
|
if (ctx->quality)
|
|
|
|
ctx->encode_config.rcParams.targetQuality = ctx->quality;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
static av_cold int nvenc_setup_h264_config(AVCodecContext *avctx)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
2016-05-25 14:05:50 +00:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_CONFIG *cc = &ctx->encode_config;
|
|
|
|
NV_ENC_CONFIG_H264 *h264 = &cc->encodeCodecConfig.h264Config;
|
|
|
|
NV_ENC_CONFIG_H264_VUI_PARAMETERS *vui = &h264->h264VUIParameters;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
vui->colourMatrix = avctx->colorspace;
|
|
|
|
vui->colourPrimaries = avctx->color_primaries;
|
|
|
|
vui->transferCharacteristics = avctx->color_trc;
|
|
|
|
vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
|
2016-05-20 22:08:06 +00:00
|
|
|
|| ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
vui->colourDescriptionPresentFlag =
|
2016-05-20 14:49:24 +00:00
|
|
|
(avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
vui->videoSignalTypePresentFlag =
|
|
|
|
(vui->colourDescriptionPresentFlag
|
|
|
|
|| vui->videoFormat != 5
|
|
|
|
|| vui->videoFullRangeFlag != 0);
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
h264->sliceMode = 3;
|
|
|
|
h264->sliceModeData = 1;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
h264->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
|
2016-05-25 16:39:54 +00:00
|
|
|
h264->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
|
2016-12-30 21:02:42 +00:00
|
|
|
h264->outputAUD = ctx->aud;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
if (avctx->refs >= 0) {
|
|
|
|
/* 0 means "let the hardware decide" */
|
|
|
|
h264->maxNumRefFrames = avctx->refs;
|
|
|
|
}
|
|
|
|
if (avctx->gop_size >= 0) {
|
|
|
|
h264->idrPeriod = cc->gopLength;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_CBR(cc->rcParams.rateControlMode)) {
|
|
|
|
h264->outputBufferingPeriodSEI = 1;
|
|
|
|
h264->outputPictureTimingSEI = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_QUALITY ||
|
|
|
|
cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP ||
|
|
|
|
cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_VBR) {
|
|
|
|
h264->adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE;
|
|
|
|
h264->fmoMode = NV_ENC_H264_FMO_DISABLE;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:26:25 +00:00
|
|
|
if (ctx->flags & NVENC_LOSSLESS) {
|
|
|
|
h264->qpPrimeYZeroTransformBypassFlag = 1;
|
|
|
|
} else {
|
|
|
|
switch(ctx->profile) {
|
|
|
|
case NV_ENC_H264_PROFILE_BASELINE:
|
2016-05-25 14:05:50 +00:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID;
|
2016-05-25 14:26:25 +00:00
|
|
|
avctx->profile = FF_PROFILE_H264_BASELINE;
|
2016-05-20 14:49:24 +00:00
|
|
|
break;
|
2016-05-25 14:26:25 +00:00
|
|
|
case NV_ENC_H264_PROFILE_MAIN:
|
2016-05-25 14:05:50 +00:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID;
|
2016-05-25 14:26:25 +00:00
|
|
|
avctx->profile = FF_PROFILE_H264_MAIN;
|
2016-05-20 14:49:24 +00:00
|
|
|
break;
|
2016-05-25 14:26:25 +00:00
|
|
|
case NV_ENC_H264_PROFILE_HIGH:
|
2016-05-25 14:05:50 +00:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID;
|
2016-05-20 14:49:24 +00:00
|
|
|
avctx->profile = FF_PROFILE_H264_HIGH;
|
2016-05-25 14:26:25 +00:00
|
|
|
break;
|
|
|
|
case NV_ENC_H264_PROFILE_HIGH_444P:
|
2016-05-25 14:05:50 +00:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
|
2016-05-20 14:49:24 +00:00
|
|
|
avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
|
2016-05-25 14:26:25 +00:00
|
|
|
break;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// force setting profile as high444p if input is AV_PIX_FMT_YUV444P
|
2016-05-20 22:08:06 +00:00
|
|
|
if (ctx->data_pix_fmt == AV_PIX_FMT_YUV444P) {
|
2016-05-25 14:05:50 +00:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
|
2016-05-20 14:49:24 +00:00
|
|
|
avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
h264->chromaFormatIDC = avctx->profile == FF_PROFILE_H264_HIGH_444_PREDICTIVE ? 3 : 1;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 15:00:52 +00:00
|
|
|
h264->level = ctx->level;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold int nvenc_setup_hevc_config(AVCodecContext *avctx)
|
|
|
|
{
|
2016-05-25 14:05:50 +00:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_CONFIG *cc = &ctx->encode_config;
|
|
|
|
NV_ENC_CONFIG_HEVC *hevc = &cc->encodeCodecConfig.hevcConfig;
|
|
|
|
NV_ENC_CONFIG_HEVC_VUI_PARAMETERS *vui = &hevc->hevcVUIParameters;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
vui->colourMatrix = avctx->colorspace;
|
|
|
|
vui->colourPrimaries = avctx->color_primaries;
|
|
|
|
vui->transferCharacteristics = avctx->color_trc;
|
|
|
|
vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
|
2016-05-20 22:08:06 +00:00
|
|
|
|| ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
vui->colourDescriptionPresentFlag =
|
2016-05-20 14:49:24 +00:00
|
|
|
(avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
vui->videoSignalTypePresentFlag =
|
|
|
|
(vui->colourDescriptionPresentFlag
|
|
|
|
|| vui->videoFormat != 5
|
|
|
|
|| vui->videoFullRangeFlag != 0);
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
hevc->sliceMode = 3;
|
|
|
|
hevc->sliceModeData = 1;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
hevc->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
|
2016-05-25 16:39:54 +00:00
|
|
|
hevc->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
|
2016-12-30 21:02:42 +00:00
|
|
|
hevc->outputAUD = ctx->aud;
|
2016-05-25 16:39:54 +00:00
|
|
|
|
|
|
|
if (avctx->refs >= 0) {
|
|
|
|
/* 0 means "let the hardware decide" */
|
|
|
|
hevc->maxNumRefFramesInDPB = avctx->refs;
|
|
|
|
}
|
|
|
|
if (avctx->gop_size >= 0) {
|
|
|
|
hevc->idrPeriod = cc->gopLength;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 16:39:54 +00:00
|
|
|
if (IS_CBR(cc->rcParams.rateControlMode)) {
|
|
|
|
hevc->outputBufferingPeriodSEI = 1;
|
|
|
|
hevc->outputPictureTimingSEI = 1;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-08-25 15:18:03 +00:00
|
|
|
switch(ctx->profile) {
|
|
|
|
case NV_ENC_HEVC_PROFILE_MAIN:
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN_GUID;
|
|
|
|
avctx->profile = FF_PROFILE_HEVC_MAIN;
|
|
|
|
break;
|
|
|
|
case NV_ENC_HEVC_PROFILE_MAIN_10:
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
|
|
|
|
avctx->profile = FF_PROFILE_HEVC_MAIN_10;
|
|
|
|
break;
|
2016-09-28 12:21:03 +00:00
|
|
|
case NV_ENC_HEVC_PROFILE_REXT:
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
|
|
|
|
avctx->profile = FF_PROFILE_HEVC_REXT;
|
|
|
|
break;
|
2016-08-25 15:18:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// force setting profile as main10 if input is 10 bit
|
|
|
|
if (IS_10BIT(ctx->data_pix_fmt)) {
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
|
|
|
|
avctx->profile = FF_PROFILE_HEVC_MAIN_10;
|
|
|
|
}
|
|
|
|
|
2016-09-28 12:21:03 +00:00
|
|
|
// force setting profile as rext if input is yuv444
|
|
|
|
if (IS_YUV444(ctx->data_pix_fmt)) {
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
|
|
|
|
avctx->profile = FF_PROFILE_HEVC_REXT;
|
|
|
|
}
|
|
|
|
|
2016-08-25 15:18:03 +00:00
|
|
|
hevc->chromaFormatIDC = IS_YUV444(ctx->data_pix_fmt) ? 3 : 1;
|
|
|
|
|
|
|
|
hevc->pixelBitDepthMinus8 = IS_10BIT(ctx->data_pix_fmt) ? 2 : 0;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 15:00:52 +00:00
|
|
|
hevc->level = ctx->level;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-25 15:06:02 +00:00
|
|
|
hevc->tier = ctx->tier;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
static av_cold int nvenc_setup_codec_config(AVCodecContext *avctx)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
2016-05-25 14:05:50 +00:00
|
|
|
return nvenc_setup_h264_config(avctx);
|
|
|
|
case AV_CODEC_ID_HEVC:
|
2016-05-20 14:49:24 +00:00
|
|
|
return nvenc_setup_hevc_config(avctx);
|
|
|
|
/* Earlier switch/case will return if unknown codec is passed. */
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold int nvenc_setup_encoder(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
NV_ENC_PRESET_CONFIG preset_config = { 0 };
|
|
|
|
NVENCSTATUS nv_status = NV_ENC_SUCCESS;
|
|
|
|
AVCPBProperties *cpb_props;
|
|
|
|
int res = 0;
|
|
|
|
int dw, dh;
|
|
|
|
|
|
|
|
ctx->encode_config.version = NV_ENC_CONFIG_VER;
|
|
|
|
ctx->init_encode_params.version = NV_ENC_INITIALIZE_PARAMS_VER;
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
ctx->init_encode_params.encodeHeight = avctx->height;
|
|
|
|
ctx->init_encode_params.encodeWidth = avctx->width;
|
|
|
|
|
|
|
|
ctx->init_encode_params.encodeConfig = &ctx->encode_config;
|
|
|
|
|
|
|
|
nvenc_map_preset(ctx);
|
|
|
|
|
|
|
|
preset_config.version = NV_ENC_PRESET_CONFIG_VER;
|
|
|
|
preset_config.presetCfg.version = NV_ENC_CONFIG_VER;
|
2015-03-24 04:34:59 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
nv_status = p_nvenc->nvEncGetEncodePresetConfig(ctx->nvencoder,
|
|
|
|
ctx->init_encode_params.encodeGUID,
|
|
|
|
ctx->init_encode_params.presetGUID,
|
|
|
|
&preset_config);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS)
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Cannot get the preset configuration");
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
memcpy(&ctx->encode_config, &preset_config.presetCfg, sizeof(ctx->encode_config));
|
|
|
|
|
|
|
|
ctx->encode_config.version = NV_ENC_CONFIG_VER;
|
2015-01-26 12:28:22 +00:00
|
|
|
|
2016-11-27 00:46:06 +00:00
|
|
|
dw = avctx->width;
|
|
|
|
dh = avctx->height;
|
|
|
|
if (avctx->sample_aspect_ratio.num > 0 && avctx->sample_aspect_ratio.den > 0) {
|
|
|
|
dw*= avctx->sample_aspect_ratio.num;
|
|
|
|
dh*= avctx->sample_aspect_ratio.den;
|
|
|
|
}
|
|
|
|
av_reduce(&dw, &dh, dw, dh, 1024 * 1024);
|
|
|
|
ctx->init_encode_params.darHeight = dh;
|
|
|
|
ctx->init_encode_params.darWidth = dw;
|
2015-01-26 12:28:22 +00:00
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
ctx->init_encode_params.frameRateNum = avctx->time_base.den;
|
|
|
|
ctx->init_encode_params.frameRateDen = avctx->time_base.num * avctx->ticks_per_frame;
|
|
|
|
|
|
|
|
ctx->init_encode_params.enableEncodeAsync = 0;
|
|
|
|
ctx->init_encode_params.enablePTD = 1;
|
|
|
|
|
2016-12-30 21:04:31 +00:00
|
|
|
if (ctx->bluray_compat) {
|
|
|
|
ctx->aud = 1;
|
|
|
|
avctx->refs = FFMIN(FFMAX(avctx->refs, 0), 6);
|
|
|
|
avctx->max_b_frames = FFMIN(avctx->max_b_frames, 3);
|
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
|
|
|
/* maximum level depends on used resolution */
|
|
|
|
break;
|
|
|
|
case AV_CODEC_ID_HEVC:
|
|
|
|
ctx->level = NV_ENC_LEVEL_HEVC_51;
|
|
|
|
ctx->tier = NV_ENC_TIER_HEVC_HIGH;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-01-26 12:28:21 +00:00
|
|
|
if (avctx->gop_size > 0) {
|
|
|
|
if (avctx->max_b_frames >= 0) {
|
2016-06-21 19:55:20 +00:00
|
|
|
/* 0 is intra-only, 1 is I/P only, 2 is one B-Frame, 3 two B-frames, and so on. */
|
2015-01-26 12:28:21 +00:00
|
|
|
ctx->encode_config.frameIntervalP = avctx->max_b_frames + 1;
|
|
|
|
}
|
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
ctx->encode_config.gopLength = avctx->gop_size;
|
2016-05-20 14:49:24 +00:00
|
|
|
} else if (avctx->gop_size == 0) {
|
|
|
|
ctx->encode_config.frameIntervalP = 0;
|
|
|
|
ctx->encode_config.gopLength = 1;
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
2016-05-31 16:59:35 +00:00
|
|
|
ctx->initial_pts[0] = AV_NOPTS_VALUE;
|
|
|
|
ctx->initial_pts[1] = AV_NOPTS_VALUE;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 11:17:43 +00:00
|
|
|
nvenc_recalc_surfaces(avctx);
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
nvenc_setup_rate_control(avctx);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2015-07-27 19:14:31 +00:00
|
|
|
if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
|
2014-11-29 23:04:37 +00:00
|
|
|
ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD;
|
|
|
|
} else {
|
|
|
|
ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME;
|
|
|
|
}
|
|
|
|
|
2016-05-25 14:05:50 +00:00
|
|
|
res = nvenc_setup_codec_config(avctx);
|
2016-05-20 14:49:24 +00:00
|
|
|
if (res)
|
|
|
|
return res;
|
2016-03-04 09:00:48 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
nv_status = p_nvenc->nvEncInitializeEncoder(ctx->nvencoder, &ctx->init_encode_params);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 15:37:00 +00:00
|
|
|
return nvenc_print_error(avctx, nv_status, "InitializeEncoder failed");
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
if (ctx->encode_config.frameIntervalP > 1)
|
|
|
|
avctx->has_b_frames = 2;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
if (ctx->encode_config.rcParams.averageBitRate > 0)
|
|
|
|
avctx->bit_rate = ctx->encode_config.rcParams.averageBitRate;
|
2015-12-14 09:27:36 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
cpb_props = ff_add_cpb_side_data(avctx);
|
|
|
|
if (!cpb_props)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
cpb_props->max_bitrate = ctx->encode_config.rcParams.maxBitRate;
|
|
|
|
cpb_props->avg_bitrate = avctx->bit_rate;
|
|
|
|
cpb_props->buffer_size = ctx->encode_config.rcParams.vbvBufferSize;
|
2015-04-01 22:04:07 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2016-03-30 10:03:59 +00:00
|
|
|
|
2016-11-25 19:11:45 +00:00
|
|
|
static NV_ENC_BUFFER_FORMAT nvenc_map_buffer_format(enum AVPixelFormat pix_fmt)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
2016-11-25 19:11:45 +00:00
|
|
|
switch (pix_fmt) {
|
2016-05-20 14:49:24 +00:00
|
|
|
case AV_PIX_FMT_YUV420P:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YV12_PL;
|
2016-05-20 14:49:24 +00:00
|
|
|
case AV_PIX_FMT_NV12:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_NV12_PL;
|
2016-08-25 15:18:03 +00:00
|
|
|
case AV_PIX_FMT_P010:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YUV420_10BIT;
|
2016-05-20 14:49:24 +00:00
|
|
|
case AV_PIX_FMT_YUV444P:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YUV444_PL;
|
2016-08-25 15:18:03 +00:00
|
|
|
case AV_PIX_FMT_YUV444P16:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YUV444_10BIT;
|
2016-09-07 13:35:14 +00:00
|
|
|
case AV_PIX_FMT_0RGB32:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_ARGB;
|
2016-09-07 13:35:14 +00:00
|
|
|
case AV_PIX_FMT_0BGR32:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_ABGR;
|
2016-05-20 14:49:24 +00:00
|
|
|
default:
|
2016-11-25 19:11:45 +00:00
|
|
|
return NV_ENC_BUFFER_FORMAT_UNDEFINED;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2016-11-25 19:11:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold int nvenc_alloc_surface(AVCodecContext *avctx, int idx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
NV_ENC_CREATE_BITSTREAM_BUFFER allocOut = { 0 };
|
|
|
|
allocOut.version = NV_ENC_CREATE_BITSTREAM_BUFFER_VER;
|
2015-12-14 09:27:36 +00:00
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
|
|
|
ctx->surfaces[idx].in_ref = av_frame_alloc();
|
|
|
|
if (!ctx->surfaces[idx].in_ref)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
} else {
|
|
|
|
NV_ENC_CREATE_INPUT_BUFFER allocSurf = { 0 };
|
2016-11-25 19:11:45 +00:00
|
|
|
|
|
|
|
ctx->surfaces[idx].format = nvenc_map_buffer_format(ctx->data_pix_fmt);
|
|
|
|
if (ctx->surfaces[idx].format == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
|
|
|
|
av_get_pix_fmt_name(ctx->data_pix_fmt));
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
allocSurf.version = NV_ENC_CREATE_INPUT_BUFFER_VER;
|
|
|
|
allocSurf.width = (avctx->width + 31) & ~31;
|
|
|
|
allocSurf.height = (avctx->height + 31) & ~31;
|
|
|
|
allocSurf.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED;
|
|
|
|
allocSurf.bufferFmt = ctx->surfaces[idx].format;
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncCreateInputBuffer(ctx->nvencoder, &allocSurf);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
return nvenc_print_error(avctx, nv_status, "CreateInputBuffer failed");
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->surfaces[idx].input_surface = allocSurf.inputBuffer;
|
|
|
|
ctx->surfaces[idx].width = allocSurf.width;
|
|
|
|
ctx->surfaces[idx].height = allocSurf.height;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2015-04-01 22:04:07 +00:00
|
|
|
|
2016-05-20 15:37:00 +00:00
|
|
|
ctx->surfaces[idx].lockCount = 0;
|
2016-03-30 10:03:59 +00:00
|
|
|
|
2016-06-21 19:55:20 +00:00
|
|
|
/* 1MB is large enough to hold most output frames.
|
|
|
|
* NVENC increases this automaticaly if it is not enough. */
|
2016-05-20 14:49:24 +00:00
|
|
|
allocOut.size = 1024 * 1024;
|
2015-04-04 11:34:14 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
allocOut.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED;
|
2015-04-04 11:34:14 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
nv_status = p_nvenc->nvEncCreateBitstreamBuffer(ctx->nvencoder, &allocOut);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 15:37:00 +00:00
|
|
|
int err = nvenc_print_error(avctx, nv_status, "CreateBitstreamBuffer failed");
|
2016-05-20 22:08:06 +00:00
|
|
|
if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
|
|
|
|
p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[idx].input_surface);
|
|
|
|
av_frame_free(&ctx->surfaces[idx].in_ref);
|
2016-05-20 15:37:00 +00:00
|
|
|
return err;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2015-04-04 11:34:14 +00:00
|
|
|
|
2016-05-20 15:37:00 +00:00
|
|
|
ctx->surfaces[idx].output_surface = allocOut.bitstreamBuffer;
|
|
|
|
ctx->surfaces[idx].size = allocOut.size;
|
2015-04-04 11:34:14 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
static av_cold int nvenc_setup_surfaces(AVCodecContext *avctx)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 16:57:11 +00:00
|
|
|
int i, res;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 10:07:34 +00:00
|
|
|
ctx->surfaces = av_mallocz_array(ctx->nb_surfaces, sizeof(*ctx->surfaces));
|
|
|
|
if (!ctx->surfaces)
|
2016-05-20 14:49:24 +00:00
|
|
|
return AVERROR(ENOMEM);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 10:07:34 +00:00
|
|
|
ctx->timestamp_list = av_fifo_alloc(ctx->nb_surfaces * sizeof(int64_t));
|
2016-05-20 16:13:20 +00:00
|
|
|
if (!ctx->timestamp_list)
|
|
|
|
return AVERROR(ENOMEM);
|
2016-05-29 10:07:34 +00:00
|
|
|
ctx->output_surface_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
|
2016-05-20 16:13:20 +00:00
|
|
|
if (!ctx->output_surface_queue)
|
|
|
|
return AVERROR(ENOMEM);
|
2016-05-29 10:07:34 +00:00
|
|
|
ctx->output_surface_ready_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
|
2016-05-20 16:13:20 +00:00
|
|
|
if (!ctx->output_surface_ready_queue)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
|
2016-05-29 10:07:34 +00:00
|
|
|
for (i = 0; i < ctx->nb_surfaces; i++) {
|
2016-05-25 16:57:11 +00:00
|
|
|
if ((res = nvenc_alloc_surface(avctx, i)) < 0)
|
2016-05-20 14:49:24 +00:00
|
|
|
return res;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
static av_cold int nvenc_setup_extradata(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
uint32_t outSize = 0;
|
|
|
|
char tmpHeader[256];
|
|
|
|
NV_ENC_SEQUENCE_PARAM_PAYLOAD payload = { 0 };
|
|
|
|
payload.version = NV_ENC_SEQUENCE_PARAM_PAYLOAD_VER;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
payload.spsppsBuffer = tmpHeader;
|
|
|
|
payload.inBufferSize = sizeof(tmpHeader);
|
|
|
|
payload.outSPSPPSPayloadSize = &outSize;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
nv_status = p_nvenc->nvEncGetSequenceParams(ctx->nvencoder, &payload);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 15:37:00 +00:00
|
|
|
return nvenc_print_error(avctx, nv_status, "GetSequenceParams failed");
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
avctx->extradata_size = outSize;
|
|
|
|
avctx->extradata = av_mallocz(outSize + AV_INPUT_BUFFER_PADDING_SIZE);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
if (!avctx->extradata) {
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
memcpy(avctx->extradata, tmpHeader, outSize);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
av_cold int ff_nvenc_encode_close(AVCodecContext *avctx)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
2016-05-25 16:57:11 +00:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-20 14:49:24 +00:00
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
int i;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
/* the encoder has to be flushed before it can be closed */
|
|
|
|
if (ctx->nvencoder) {
|
|
|
|
NV_ENC_PIC_PARAMS params = { .version = NV_ENC_PIC_PARAMS_VER,
|
|
|
|
.encodePicFlags = NV_ENC_PIC_FLAG_EOS };
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
p_nvenc->nvEncEncodePicture(ctx->nvencoder, ¶ms);
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
2015-05-30 14:40:13 +00:00
|
|
|
|
2016-05-20 16:13:20 +00:00
|
|
|
av_fifo_freep(&ctx->timestamp_list);
|
|
|
|
av_fifo_freep(&ctx->output_surface_ready_queue);
|
|
|
|
av_fifo_freep(&ctx->output_surface_queue);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
if (ctx->surfaces && avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
2016-05-29 10:07:34 +00:00
|
|
|
for (i = 0; i < ctx->nb_surfaces; ++i) {
|
2016-05-20 22:08:06 +00:00
|
|
|
if (ctx->surfaces[i].input_surface) {
|
|
|
|
p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->surfaces[i].in_map.mappedResource);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (i = 0; i < ctx->nb_registered_frames; i++) {
|
|
|
|
if (ctx->registered_frames[i].regptr)
|
|
|
|
p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[i].regptr);
|
|
|
|
}
|
|
|
|
ctx->nb_registered_frames = 0;
|
|
|
|
}
|
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
if (ctx->surfaces) {
|
2016-05-29 10:07:34 +00:00
|
|
|
for (i = 0; i < ctx->nb_surfaces; ++i) {
|
2016-05-25 16:57:11 +00:00
|
|
|
if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
|
|
|
|
p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[i].input_surface);
|
|
|
|
av_frame_free(&ctx->surfaces[i].in_ref);
|
|
|
|
p_nvenc->nvEncDestroyBitstreamBuffer(ctx->nvencoder, ctx->surfaces[i].output_surface);
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
2016-05-20 16:13:20 +00:00
|
|
|
av_freep(&ctx->surfaces);
|
2016-05-29 10:07:34 +00:00
|
|
|
ctx->nb_surfaces = 0;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-25 16:57:11 +00:00
|
|
|
if (ctx->nvencoder)
|
|
|
|
p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
|
2014-11-29 23:04:37 +00:00
|
|
|
ctx->nvencoder = NULL;
|
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
if (ctx->cu_context_internal)
|
2016-10-10 10:55:59 +00:00
|
|
|
dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal);
|
2016-05-20 22:08:06 +00:00
|
|
|
ctx->cu_context = ctx->cu_context_internal = NULL;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-10-10 10:55:59 +00:00
|
|
|
nvenc_free_functions(&dl_fn->nvenc_dl);
|
|
|
|
cuda_free_functions(&dl_fn->cuda_dl);
|
2016-05-25 16:57:11 +00:00
|
|
|
|
|
|
|
dl_fn->nvenc_device_count = 0;
|
|
|
|
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Nvenc unloaded\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
|
|
|
|
{
|
2016-05-29 12:23:26 +00:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
int ret;
|
2016-05-25 16:57:11 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
|
|
|
AVHWFramesContext *frames_ctx;
|
|
|
|
if (!avctx->hw_frames_ctx) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR,
|
|
|
|
"hw_frames_ctx must be set when using GPU frames as input\n");
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
|
|
|
|
ctx->data_pix_fmt = frames_ctx->sw_format;
|
|
|
|
} else {
|
|
|
|
ctx->data_pix_fmt = avctx->pix_fmt;
|
|
|
|
}
|
2016-05-25 16:57:11 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_load_libraries(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 16:57:11 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_setup_device(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 16:57:11 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_setup_encoder(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 16:57:11 +00:00
|
|
|
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_setup_surfaces(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 16:57:11 +00:00
|
|
|
|
|
|
|
if (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) {
|
2016-05-29 12:23:26 +00:00
|
|
|
if ((ret = nvenc_setup_extradata(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 16:57:11 +00:00
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-20 15:37:00 +00:00
|
|
|
static NvencSurface *get_free_frame(NvencContext *ctx)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2016-05-29 10:07:34 +00:00
|
|
|
for (i = 0; i < ctx->nb_surfaces; ++i) {
|
2016-05-20 15:37:00 +00:00
|
|
|
if (!ctx->surfaces[i].lockCount) {
|
|
|
|
ctx->surfaces[i].lockCount = 1;
|
|
|
|
return &ctx->surfaces[i];
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-09-07 13:49:28 +00:00
|
|
|
static int nvenc_copy_frame(AVCodecContext *avctx, NvencSurface *nv_surface,
|
|
|
|
NV_ENC_LOCK_INPUT_BUFFER *lock_buffer_params, const AVFrame *frame)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
2016-09-07 13:49:28 +00:00
|
|
|
int dst_linesize[4] = {
|
|
|
|
lock_buffer_params->pitch,
|
|
|
|
lock_buffer_params->pitch,
|
|
|
|
lock_buffer_params->pitch,
|
|
|
|
lock_buffer_params->pitch
|
|
|
|
};
|
|
|
|
uint8_t *dst_data[4];
|
|
|
|
int ret;
|
2016-08-25 15:18:03 +00:00
|
|
|
|
2016-09-07 13:49:28 +00:00
|
|
|
if (frame->format == AV_PIX_FMT_YUV420P)
|
|
|
|
dst_linesize[1] = dst_linesize[2] >>= 1;
|
2016-08-25 15:18:03 +00:00
|
|
|
|
2016-09-07 13:49:28 +00:00
|
|
|
ret = av_image_fill_pointers(dst_data, frame->format, nv_surface->height,
|
|
|
|
lock_buffer_params->bufferDataPtr, dst_linesize);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2016-08-25 15:18:03 +00:00
|
|
|
|
2016-09-07 13:49:28 +00:00
|
|
|
if (frame->format == AV_PIX_FMT_YUV420P)
|
|
|
|
FFSWAP(uint8_t*, dst_data[1], dst_data[2]);
|
2016-08-25 15:18:03 +00:00
|
|
|
|
2016-09-07 13:49:28 +00:00
|
|
|
av_image_copy(dst_data, dst_linesize,
|
|
|
|
(const uint8_t**)frame->data, frame->linesize, frame->format,
|
2016-09-08 17:08:31 +00:00
|
|
|
avctx->width, avctx->height);
|
2016-05-20 14:49:24 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
static int nvenc_find_free_reg_resource(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (ctx->nb_registered_frames == FF_ARRAY_ELEMS(ctx->registered_frames)) {
|
|
|
|
for (i = 0; i < ctx->nb_registered_frames; i++) {
|
|
|
|
if (!ctx->registered_frames[i].mapped) {
|
|
|
|
if (ctx->registered_frames[i].regptr) {
|
|
|
|
p_nvenc->nvEncUnregisterResource(ctx->nvencoder,
|
|
|
|
ctx->registered_frames[i].regptr);
|
|
|
|
ctx->registered_frames[i].regptr = NULL;
|
|
|
|
}
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
return ctx->nb_registered_frames++;
|
|
|
|
}
|
|
|
|
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Too many registered CUDA frames\n");
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
AVHWFramesContext *frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
|
|
|
|
NV_ENC_REGISTER_RESOURCE reg;
|
|
|
|
int i, idx, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < ctx->nb_registered_frames; i++) {
|
|
|
|
if (ctx->registered_frames[i].ptr == (CUdeviceptr)frame->data[0])
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
idx = nvenc_find_free_reg_resource(avctx);
|
|
|
|
if (idx < 0)
|
|
|
|
return idx;
|
|
|
|
|
|
|
|
reg.version = NV_ENC_REGISTER_RESOURCE_VER;
|
|
|
|
reg.resourceType = NV_ENC_INPUT_RESOURCE_TYPE_CUDADEVICEPTR;
|
|
|
|
reg.width = frames_ctx->width;
|
|
|
|
reg.height = frames_ctx->height;
|
|
|
|
reg.pitch = frame->linesize[0];
|
|
|
|
reg.resourceToRegister = frame->data[0];
|
|
|
|
|
2016-11-25 19:11:45 +00:00
|
|
|
reg.bufferFormat = nvenc_map_buffer_format(frames_ctx->sw_format);
|
|
|
|
if (reg.bufferFormat == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
|
|
|
|
av_get_pix_fmt_name(frames_ctx->sw_format));
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
ret = p_nvenc->nvEncRegisterResource(ctx->nvencoder, ®);
|
|
|
|
if (ret != NV_ENC_SUCCESS) {
|
|
|
|
nvenc_print_error(avctx, ret, "Error registering an input resource");
|
|
|
|
return AVERROR_UNKNOWN;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->registered_frames[idx].ptr = (CUdeviceptr)frame->data[0];
|
|
|
|
ctx->registered_frames[idx].regptr = reg.registeredResource;
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
static int nvenc_upload_frame(AVCodecContext *avctx, const AVFrame *frame,
|
2016-05-20 15:37:00 +00:00
|
|
|
NvencSurface *nvenc_frame)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
int res;
|
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
|
|
|
int reg_idx = nvenc_register_frame(avctx, frame);
|
|
|
|
if (reg_idx < 0) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Could not register an input CUDA frame\n");
|
|
|
|
return reg_idx;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
res = av_frame_ref(nvenc_frame->in_ref, frame);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
nvenc_frame->in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER;
|
|
|
|
nvenc_frame->in_map.registeredResource = ctx->registered_frames[reg_idx].regptr;
|
|
|
|
nv_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &nvenc_frame->in_map);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
av_frame_unref(nvenc_frame->in_ref);
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Error mapping an input resource");
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
ctx->registered_frames[reg_idx].mapped = 1;
|
|
|
|
nvenc_frame->reg_idx = reg_idx;
|
|
|
|
nvenc_frame->input_surface = nvenc_frame->in_map.mappedResource;
|
2017-02-10 14:00:21 +00:00
|
|
|
nvenc_frame->format = nvenc_frame->in_map.mappedBufferFmt;
|
2016-09-07 16:15:22 +00:00
|
|
|
nvenc_frame->pitch = frame->linesize[0];
|
2016-05-20 22:08:06 +00:00
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
NV_ENC_LOCK_INPUT_BUFFER lockBufferParams = { 0 };
|
2016-05-20 14:49:24 +00:00
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
lockBufferParams.version = NV_ENC_LOCK_INPUT_BUFFER_VER;
|
|
|
|
lockBufferParams.inputBuffer = nvenc_frame->input_surface;
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncLockInputBuffer(ctx->nvencoder, &lockBufferParams);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Failed locking nvenc input buffer");
|
|
|
|
}
|
|
|
|
|
2016-09-07 16:15:22 +00:00
|
|
|
nvenc_frame->pitch = lockBufferParams.pitch;
|
2016-05-20 22:08:06 +00:00
|
|
|
res = nvenc_copy_frame(avctx, nvenc_frame, &lockBufferParams, frame);
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncUnlockInputBuffer(ctx->nvencoder, nvenc_frame->input_surface);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Failed unlocking input buffer!");
|
|
|
|
}
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void nvenc_codec_specific_pic_params(AVCodecContext *avctx,
|
2016-05-29 12:50:06 +00:00
|
|
|
NV_ENC_PIC_PARAMS *params)
|
2016-05-20 14:49:24 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
2016-05-29 12:50:06 +00:00
|
|
|
params->codecPicParams.h264PicParams.sliceMode =
|
|
|
|
ctx->encode_config.encodeCodecConfig.h264Config.sliceMode;
|
|
|
|
params->codecPicParams.h264PicParams.sliceModeData =
|
|
|
|
ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
|
2016-05-20 14:49:24 +00:00
|
|
|
break;
|
2016-05-29 12:50:06 +00:00
|
|
|
case AV_CODEC_ID_HEVC:
|
|
|
|
params->codecPicParams.hevcPicParams.sliceMode =
|
|
|
|
ctx->encode_config.encodeCodecConfig.hevcConfig.sliceMode;
|
|
|
|
params->codecPicParams.hevcPicParams.sliceModeData =
|
|
|
|
ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
|
|
|
|
break;
|
2016-05-20 14:49:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-29 12:50:06 +00:00
|
|
|
static inline void timestamp_queue_enqueue(AVFifoBuffer* queue, int64_t timestamp)
|
|
|
|
{
|
|
|
|
av_fifo_generic_write(queue, ×tamp, sizeof(timestamp), NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int64_t timestamp_queue_dequeue(AVFifoBuffer* queue)
|
|
|
|
{
|
|
|
|
int64_t timestamp = AV_NOPTS_VALUE;
|
|
|
|
if (av_fifo_size(queue) > 0)
|
|
|
|
av_fifo_generic_read(queue, ×tamp, sizeof(timestamp), NULL);
|
|
|
|
|
|
|
|
return timestamp;
|
|
|
|
}
|
|
|
|
|
2016-05-29 12:34:38 +00:00
|
|
|
static int nvenc_set_timestamp(AVCodecContext *avctx,
|
|
|
|
NV_ENC_LOCK_BITSTREAM *params,
|
|
|
|
AVPacket *pkt)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
|
|
|
pkt->pts = params->outputTimeStamp;
|
|
|
|
|
2016-05-31 16:59:35 +00:00
|
|
|
/* generate the first dts by linearly extrapolating the
|
|
|
|
* first two pts values to the past */
|
|
|
|
if (avctx->max_b_frames > 0 && !ctx->first_packet_output &&
|
|
|
|
ctx->initial_pts[1] != AV_NOPTS_VALUE) {
|
|
|
|
int64_t ts0 = ctx->initial_pts[0], ts1 = ctx->initial_pts[1];
|
|
|
|
int64_t delta;
|
|
|
|
|
|
|
|
if ((ts0 < 0 && ts1 > INT64_MAX + ts0) ||
|
|
|
|
(ts0 > 0 && ts1 < INT64_MIN + ts0))
|
|
|
|
return AVERROR(ERANGE);
|
|
|
|
delta = ts1 - ts0;
|
2016-05-29 12:34:38 +00:00
|
|
|
|
2016-05-31 16:59:35 +00:00
|
|
|
if ((delta < 0 && ts0 > INT64_MAX + delta) ||
|
|
|
|
(delta > 0 && ts0 < INT64_MIN + delta))
|
|
|
|
return AVERROR(ERANGE);
|
|
|
|
pkt->dts = ts0 - delta;
|
|
|
|
|
|
|
|
ctx->first_packet_output = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-29 12:34:38 +00:00
|
|
|
|
2016-05-31 16:59:35 +00:00
|
|
|
pkt->dts = timestamp_queue_dequeue(ctx->timestamp_list);
|
2016-05-29 12:34:38 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-20 15:37:00 +00:00
|
|
|
static int process_output_surface(AVCodecContext *avctx, AVPacket *pkt, NvencSurface *tmpoutsurf)
|
2014-11-29 23:04:37 +00:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
2015-03-24 04:34:59 +00:00
|
|
|
uint32_t slice_mode_data;
|
2016-08-28 16:19:21 +00:00
|
|
|
uint32_t *slice_offsets = NULL;
|
2014-11-29 23:04:37 +00:00
|
|
|
NV_ENC_LOCK_BITSTREAM lock_params = { 0 };
|
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
int res = 0;
|
|
|
|
|
2016-03-07 23:47:56 +00:00
|
|
|
enum AVPictureType pict_type;
|
|
|
|
|
2015-03-24 04:34:59 +00:00
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
|
|
|
slice_mode_data = ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
|
|
|
|
break;
|
|
|
|
case AV_CODEC_ID_H265:
|
|
|
|
slice_mode_data = ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
|
|
|
|
break;
|
|
|
|
default:
|
2015-09-11 09:07:10 +00:00
|
|
|
av_log(avctx, AV_LOG_ERROR, "Unknown codec name\n");
|
2015-03-24 04:34:59 +00:00
|
|
|
res = AVERROR(EINVAL);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
slice_offsets = av_mallocz(slice_mode_data * sizeof(*slice_offsets));
|
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
if (!slice_offsets)
|
2016-05-29 12:34:38 +00:00
|
|
|
goto error;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
|
|
|
lock_params.version = NV_ENC_LOCK_BITSTREAM_VER;
|
|
|
|
|
|
|
|
lock_params.doNotWait = 0;
|
|
|
|
lock_params.outputBitstream = tmpoutsurf->output_surface;
|
|
|
|
lock_params.sliceOffsets = slice_offsets;
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncLockBitstream(ctx->nvencoder, &lock_params);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 15:37:00 +00:00
|
|
|
res = nvenc_print_error(avctx, nv_status, "Failed locking bitstream buffer");
|
2014-11-29 23:04:37 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2015-09-11 09:07:10 +00:00
|
|
|
if (res = ff_alloc_packet2(avctx, pkt, lock_params.bitstreamSizeInBytes,0)) {
|
2014-11-29 23:04:37 +00:00
|
|
|
p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(pkt->data, lock_params.bitstreamBufferPtr, lock_params.bitstreamSizeInBytes);
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS)
|
2016-05-20 15:37:00 +00:00
|
|
|
nvenc_print_error(avctx, nv_status, "Failed unlocking bitstream buffer, expect the gates of mordor to open");
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-20 22:08:06 +00:00
|
|
|
|
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
|
|
|
p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, tmpoutsurf->in_map.mappedResource);
|
|
|
|
av_frame_unref(tmpoutsurf->in_ref);
|
|
|
|
ctx->registered_frames[tmpoutsurf->reg_idx].mapped = 0;
|
|
|
|
|
|
|
|
tmpoutsurf->input_surface = NULL;
|
|
|
|
}
|
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
switch (lock_params.pictureType) {
|
|
|
|
case NV_ENC_PIC_TYPE_IDR:
|
|
|
|
pkt->flags |= AV_PKT_FLAG_KEY;
|
|
|
|
case NV_ENC_PIC_TYPE_I:
|
2016-03-07 23:47:56 +00:00
|
|
|
pict_type = AV_PICTURE_TYPE_I;
|
2014-11-29 23:04:37 +00:00
|
|
|
break;
|
|
|
|
case NV_ENC_PIC_TYPE_P:
|
2016-03-07 23:47:56 +00:00
|
|
|
pict_type = AV_PICTURE_TYPE_P;
|
2014-11-29 23:04:37 +00:00
|
|
|
break;
|
|
|
|
case NV_ENC_PIC_TYPE_B:
|
2016-03-07 23:47:56 +00:00
|
|
|
pict_type = AV_PICTURE_TYPE_B;
|
2014-11-29 23:04:37 +00:00
|
|
|
break;
|
|
|
|
case NV_ENC_PIC_TYPE_BI:
|
2016-03-07 23:47:56 +00:00
|
|
|
pict_type = AV_PICTURE_TYPE_BI;
|
2014-11-29 23:04:37 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Unknown picture type encountered, expect the output to be broken.\n");
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Please report this error and include as much information on how to reproduce it as possible.\n");
|
|
|
|
res = AVERROR_EXTERNAL;
|
|
|
|
goto error;
|
2016-03-07 23:47:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#if FF_API_CODED_FRAME
|
|
|
|
FF_DISABLE_DEPRECATION_WARNINGS
|
|
|
|
avctx->coded_frame->pict_type = pict_type;
|
2015-07-15 17:41:22 +00:00
|
|
|
FF_ENABLE_DEPRECATION_WARNINGS
|
|
|
|
#endif
|
2016-03-07 23:47:56 +00:00
|
|
|
|
|
|
|
ff_side_data_set_encoder_stats(pkt,
|
|
|
|
(lock_params.frameAvgQP - 1) * FF_QP2LAMBDA, NULL, 0, pict_type);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:34:38 +00:00
|
|
|
res = nvenc_set_timestamp(avctx, &lock_params, pkt);
|
|
|
|
if (res < 0)
|
|
|
|
goto error2;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
|
|
|
av_free(slice_offsets);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
2016-05-29 12:34:38 +00:00
|
|
|
timestamp_queue_dequeue(ctx->timestamp_list);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:34:38 +00:00
|
|
|
error2:
|
2014-11-29 23:04:37 +00:00
|
|
|
av_free(slice_offsets);
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2016-05-29 12:50:06 +00:00
|
|
|
static int output_ready(AVCodecContext *avctx, int flush)
|
2016-05-20 16:13:20 +00:00
|
|
|
{
|
2016-05-29 12:50:06 +00:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-20 16:13:20 +00:00
|
|
|
int nb_ready, nb_pending;
|
|
|
|
|
2016-05-31 16:59:35 +00:00
|
|
|
/* when B-frames are enabled, we wait for two initial timestamps to
|
|
|
|
* calculate the first dts */
|
|
|
|
if (!flush && avctx->max_b_frames > 0 &&
|
|
|
|
(ctx->initial_pts[0] == AV_NOPTS_VALUE || ctx->initial_pts[1] == AV_NOPTS_VALUE))
|
|
|
|
return 0;
|
|
|
|
|
2016-05-20 16:13:20 +00:00
|
|
|
nb_ready = av_fifo_size(ctx->output_surface_ready_queue) / sizeof(NvencSurface*);
|
|
|
|
nb_pending = av_fifo_size(ctx->output_surface_queue) / sizeof(NvencSurface*);
|
2016-05-29 12:50:06 +00:00
|
|
|
if (flush)
|
|
|
|
return nb_ready > 0;
|
|
|
|
return (nb_ready > 0) && (nb_ready + nb_pending >= ctx->async_depth);
|
2016-05-20 16:13:20 +00:00
|
|
|
}
|
|
|
|
|
2016-05-25 13:04:28 +00:00
|
|
|
int ff_nvenc_encode_frame(AVCodecContext *avctx, AVPacket *pkt,
|
2016-05-29 12:50:06 +00:00
|
|
|
const AVFrame *frame, int *got_packet)
|
2014-11-29 23:04:37 +00:00
|
|
|
{
|
|
|
|
NVENCSTATUS nv_status;
|
2017-02-13 21:59:46 +00:00
|
|
|
CUresult cu_res;
|
|
|
|
CUcontext dummy;
|
2016-05-20 15:37:00 +00:00
|
|
|
NvencSurface *tmpoutsurf, *inSurf;
|
|
|
|
int res;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
NV_ENC_PIC_PARAMS pic_params = { 0 };
|
|
|
|
pic_params.version = NV_ENC_PIC_PARAMS_VER;
|
|
|
|
|
|
|
|
if (frame) {
|
2016-05-20 14:49:24 +00:00
|
|
|
inSurf = get_free_frame(ctx);
|
2016-05-29 12:50:06 +00:00
|
|
|
if (!inSurf) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "No free surfaces\n");
|
|
|
|
return AVERROR_BUG;
|
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2017-02-13 21:59:46 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context);
|
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "cuCtxPushCurrent failed\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
res = nvenc_upload_frame(avctx, frame, inSurf);
|
2017-02-13 21:59:46 +00:00
|
|
|
|
|
|
|
cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
|
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "cuCtxPopCurrent failed\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
|
|
|
|
2016-05-20 14:49:24 +00:00
|
|
|
if (res) {
|
|
|
|
inSurf->lockCount = 0;
|
|
|
|
return res;
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
pic_params.inputBuffer = inSurf->input_surface;
|
|
|
|
pic_params.bufferFmt = inSurf->format;
|
|
|
|
pic_params.inputWidth = avctx->width;
|
|
|
|
pic_params.inputHeight = avctx->height;
|
2016-09-07 16:15:22 +00:00
|
|
|
pic_params.inputPitch = inSurf->pitch;
|
2016-05-20 15:37:00 +00:00
|
|
|
pic_params.outputBitstream = inSurf->output_surface;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2015-06-29 19:59:37 +00:00
|
|
|
if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
|
2016-05-29 12:50:06 +00:00
|
|
|
if (frame->top_field_first)
|
2014-11-29 23:04:37 +00:00
|
|
|
pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM;
|
2016-05-29 12:50:06 +00:00
|
|
|
else
|
2014-11-29 23:04:37 +00:00
|
|
|
pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP;
|
|
|
|
} else {
|
|
|
|
pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FRAME;
|
|
|
|
}
|
|
|
|
|
2016-10-12 18:51:43 +00:00
|
|
|
if (ctx->forced_idr >= 0 && frame->pict_type == AV_PICTURE_TYPE_I) {
|
|
|
|
pic_params.encodePicFlags =
|
|
|
|
ctx->forced_idr ? NV_ENC_PIC_FLAG_FORCEIDR : NV_ENC_PIC_FLAG_FORCEINTRA;
|
|
|
|
} else {
|
|
|
|
pic_params.encodePicFlags = 0;
|
|
|
|
}
|
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
pic_params.inputTimeStamp = frame->pts;
|
2016-05-20 14:49:24 +00:00
|
|
|
|
|
|
|
nvenc_codec_specific_pic_params(avctx, &pic_params);
|
2014-11-29 23:04:37 +00:00
|
|
|
} else {
|
|
|
|
pic_params.encodePicFlags = NV_ENC_PIC_FLAG_EOS;
|
|
|
|
}
|
|
|
|
|
2017-02-13 21:59:46 +00:00
|
|
|
cu_res = dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context);
|
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "cuCtxPushCurrent failed\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
|
|
|
|
2014-11-29 23:04:37 +00:00
|
|
|
nv_status = p_nvenc->nvEncEncodePicture(ctx->nvencoder, &pic_params);
|
2017-02-13 21:59:46 +00:00
|
|
|
|
|
|
|
cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
|
|
|
|
if (cu_res != CUDA_SUCCESS) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "cuCtxPopCurrent failed\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
|
|
|
|
2016-05-29 12:50:06 +00:00
|
|
|
if (nv_status != NV_ENC_SUCCESS &&
|
|
|
|
nv_status != NV_ENC_ERR_NEED_MORE_INPUT)
|
|
|
|
return nvenc_print_error(avctx, nv_status, "EncodePicture failed!");
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:51:36 +00:00
|
|
|
if (frame) {
|
2016-05-20 16:13:20 +00:00
|
|
|
av_fifo_generic_write(ctx->output_surface_queue, &inSurf, sizeof(inSurf), NULL);
|
2016-05-29 12:51:36 +00:00
|
|
|
timestamp_queue_enqueue(ctx->timestamp_list, frame->pts);
|
2016-05-31 16:59:35 +00:00
|
|
|
|
|
|
|
if (ctx->initial_pts[0] == AV_NOPTS_VALUE)
|
|
|
|
ctx->initial_pts[0] = frame->pts;
|
|
|
|
else if (ctx->initial_pts[1] == AV_NOPTS_VALUE)
|
|
|
|
ctx->initial_pts[1] = frame->pts;
|
2016-05-29 12:51:36 +00:00
|
|
|
}
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2016-05-29 12:50:06 +00:00
|
|
|
/* all the pending buffers are now ready for output */
|
|
|
|
if (nv_status == NV_ENC_SUCCESS) {
|
2016-05-20 16:13:20 +00:00
|
|
|
while (av_fifo_size(ctx->output_surface_queue) > 0) {
|
|
|
|
av_fifo_generic_read(ctx->output_surface_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
|
|
|
|
av_fifo_generic_write(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
|
2014-11-29 23:04:37 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-29 12:50:06 +00:00
|
|
|
if (output_ready(avctx, !frame)) {
|
2016-05-20 16:13:20 +00:00
|
|
|
av_fifo_generic_read(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
2015-07-25 21:26:42 +00:00
|
|
|
res = process_output_surface(avctx, pkt, tmpoutsurf);
|
2014-11-29 23:04:37 +00:00
|
|
|
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
|
2016-05-20 15:37:00 +00:00
|
|
|
av_assert0(tmpoutsurf->lockCount);
|
|
|
|
tmpoutsurf->lockCount--;
|
2014-11-29 23:04:37 +00:00
|
|
|
|
|
|
|
*got_packet = 1;
|
|
|
|
} else {
|
|
|
|
*got_packet = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|